1. Advanced Digital Design Asynchronous Design: DI Methods by A. Steininger and M. Delvai Vienna University of Technology

2. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 2 Outline Delay Insensitive design - principle Delay Insensitive design - principle NULL-Convention Logic NULL-Convention Logic Code conditions for DI logic Code conditions for DI logic Four-State Logic Four-State Logic Evaluation of async. design styles Evaluation of async. design styles Bundled Data Bundled Data NULL-Convention Logic NULL-Convention Logic Four-State Logic Four-State Logic

3. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 3 „The control flow requires agreement between source and sink. For this purpose they need to communicate“ „The control flow requires agreement between source and sink. For this purpose they need to communicate“ Source indicates capture condition for sink. Source indicates capture condition for sink. Sink indicates issue condition for source. Sink indicates issue condition for source. Asynchronous Philosophy „HANDSHAKE“ recal l

4. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 4 Handshake Principle SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? REQ: „Data word valid, you can use it“ ACK: „Data word consumed, send the next“ recal l

5. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 5 A very Important Detail The handshake establishes a closed-loop control for the data flow between sender and receiver The handshake establishes a closed-loop control for the data flow between sender and receiver This makes operation more robust than in the synchronous (= open-loop) case This makes operation more robust than in the synchronous (= open-loop) case The art of asynchronous design is to make many of these closed loops interoperate properly The art of asynchronous design is to make many of these closed loops interoperate properly This is much more complicated than a synchronous design. This is much more complicated than a synchronous design. recal l

6. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 6 Very disappointing… For a closed loop we need to measure the quantity of interest For a closed loop we need to measure the quantity of interest So far we have not done that: So far we have not done that: We have not measured validity & consistency We have not measured validity & consistency We have used time as an indirect measure instead We have used time as an indirect measure instead Thus Bounded Delay methods do not provide the benefits of a closed loop Thus Bounded Delay methods do not provide the benefits of a closed loop BUT: Can we measure validity & consistency at all? BUT: Can we measure validity & consistency at all?

7. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 7 Criticality of ACK cannot measure „act of latching“ as an event cannot measure „act of latching“ as an event use latching command instead use latching command instead fork produces race between trigger process and next data wave fork produces race between trigger process and next data wave race is uncritical (but still exists!) race is uncritical (but still exists!) SRCSNK f(x) FF2 „latch!“ recal l

8. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 8 Criticality of REQ SRCSNK f(x) cannot use issue trigger as an event: cannot use issue trigger as an event: produces unacceptable race between data and REQ produces unacceptable race between data and REQ must introduce timer (bounded delay) must introduce timer (bounded delay) OR: find better event (downstream) OR: find better event (downstream) completion detection recal l

9. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 9 Completion Detection In order to judge when data are valid & consistent we need to be able to see when this is NOT the case In order to judge when data are valid & consistent we need to be able to see when this is NOT the case not possible with Boolean logic not possible with Boolean logic need representation for INVALID need representation for INVALID an ACK in parallel to data (bundled data) will always cause a race an ACK in parallel to data (bundled data) will always cause a race need more than two signal states for every individual bit (!) need more than two signal states for every individual bit (!) need more than one rail per bit need more than one rail per bit

10. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 10 Multi-level Logic use more than two (e.g. three) voltage levels per rail use more than two (e.g. three) voltage levels per rail allows to express „invalid“ in the currently „forbidden“ area between HI and „LO“ allows to express „invalid“ in the currently „forbidden“ area between HI and „LO“ requires two thresholds for every gate input requires two thresholds for every gate input output must be able to drive three different levels reliably output must be able to drive three different levels reliably causes substantial technological problems causes substantial technological problems not further pursued

11. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 11 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive recal l

12. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 12 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW recal l

13. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 13 Add the value NULL to the alphabet Signal X X.aX.bmeaning 00 NULL (N) 01 TRUE (T) 10 FALSE (F) 11illegal X X.a X.b two-rail coding: NULL Convention Logic „DATA“

14. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 14 TFN TTFN FFFN NNNN ANDTFNTTTN FTFN NNNN OR TF FT NN NOT NCL Functions naive approach: if any input is „N“ then output „N“

15. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 15 NCL Flow Control NULL waves enframe DATA waves NULL waves enframe DATA waves Completion detection = check wether all bits are „DATA“ (completeness of DATA) Completion detection = check wether all bits are „DATA“ (completeness of DATA) NULL TRUE FALSE TRUE NULL TRUE FALSE TRUE FALSENULL t consistent DATA

16. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 16 Still Problems … What about this situation? Fast bits may catch up with a slow bit from the previous word. The word containing the „old“ bit is considered consistent! NULL TRUE FALSE TRUE NULL TRUE FALSENULL t consistent DATA DATA NULL output

17. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 17 Solution Principle Enforce „completeness of NULL“ as well: Enforce „completeness of NULL“ as well: The output must not go to NULL before all inputs have changed to NULL The output must not go to NULL before all inputs have changed to NULL In a closed loop configuration this keeps the slow paths in synchrony with the fast ones In a closed loop configuration this keeps the slow paths in synchrony with the fast ones We need different truth table when output is NULL

18. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 18 TFN TTFN FFFN NNNN ANDTFNTTFD FFFD NDDN Two Truth Tables for DATA waves for NULL waves D … DATA (T or F) must hold output in last valid state before new input is complete need „hysteresis“ need to consider current output in truth table

19. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 19 A B Y‘ NFT NTFNTFNTF NTFNTFNTFNTFNTFNTFNTFNTFNTF NNNNTFNFFNFFFFFFFFNTTTTTTTT Y Y A B T F F N N N FN A & Feedback Gate unstable (Y  Y‘)

20. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 20 No more Problems … Have we solved the problem? YES! The output now remains at DATA with the slowest bit, thus inhibiting (via the closed loop) the fast bits to convey the next DATA wave. NULL TRUE FALSE TRUE NULL t consistent DATA DATANULL output

21. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 21 The desired hysteresis requires an NCL gate to hold its output until all inputs are DATA or all inputs are DATA or all inputs are NULL all inputs are NULL need storage capability (or feedback loop) even in combi- national gate Mem X1.a X1.b X1 X2.a X2.b X2 Y.a Y.b Y Mem NCL Gates

22. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 22 [G. Sobelmann, K. Fant: CMOS Circuit Design of Threshold Gates with Hysteresis] p- and n-stack not dual memory cell at output A NCL Gate Implementation Mem X1.a X1.b X1 X2.a X2.b X2 Y.a Y.b Y Mem figure shown for one output rail only CMOS-Transistors only but no standard cells

23. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 23 The Charme of NCL self-regulating data flow self-regulating data flow in a NULL initialized circuit a DATA front will propagate towards the output in a NULL initialized circuit a DATA front will propagate towards the output alternating waves of NULL and DATA pace the data flow (which, in some sense, forms the „clock“) alternating waves of NULL and DATA pace the data flow (which, in some sense, forms the „clock“) based on direct assessment of validity & consistency based on direct assessment of validity & consistency no delay assumptions necessary (ideally), no „worst case“, … no delay assumptions necessary (ideally), no „worst case“, … globally applicable solution globally applicable solution

24. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 24 Validity and Consistency Consistency (multiple bits @ input) Consistency (multiple bits @ input) all bits that are combined are valid and belong to the same context all bits that are combined are valid and belong to the same context Validity (single bit @ output) Validity (single bit @ output) the bit is the stable result of a combination of consistent bits the bit is the stable result of a combination of consistent bits Consistency implies validity (per definition) but NOT vice versa!

25. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 25 Val. & Consistcy. in NCL Validity: Validity: output is changed only when consistent input is available („hold“ in truth table) output is changed only when consistent input is available („hold“ in truth table) coding ensures direct transistion from valid code to another (NULL is valid but spacer only) coding ensures direct transistion from valid code to another (NULL is valid but spacer only) continuous validity continuous validity Consistency: Consistency: NULL spacer between DATA waves allows identification of context NULL spacer between DATA waves allows identification of context synchronization of context by virtue of „completeness of NULL“ condition synchronization of context by virtue of „completeness of NULL“ condition

26. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 26 What about sync. & BD? Timing ensures that every data item is both valid and consistent at the time it is used: Timing ensures that every data item is both valid and consistent at the time it is used: choice of clock period (sync) choice of clock period (sync) choice of delay values (BD) choice of delay values (BD) In contrast to NCL (temporary) invalidity of data is admitted. In contrast to NCL (temporary) invalidity of data is admitted. No explicit measures (other than timing) are taken/necessary to cope with these issues. No explicit measures (other than timing) are taken/necessary to cope with these issues.

27. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 27 synchronous model synchronous model known bounds for delays, global timing known bounds for delays, global timing bounded delay model (fundamental) bounded delay model (fundamental) known bounds for absolute delays, local timing known bounds for absolute delays, local timing scalable-delay-insensitive model scalable-delay-insensitive model bounds for relative deviation between delays known bounds for relative deviation between delays known quasi-delay-insensitive quasi-delay-insensitive output paths of a fork have same delay output paths of a fork have same delay delay insensitive delay insensitive no restrictions on delays (just finite) no restrictions on delays (just finite) Softening the restrictions recal l

28. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 28 validity & consistency directly visible validity & consistency directly visible no timing assumptions required (ideally) no timing assumptions required (ideally) „delay insensitive“ (ideally) „delay insensitive“ (ideally) suitable for CMOS implementation suitable for CMOS implementation  coding of one bit on two rails  2 memory cells per combinational output  efficiency: 50% of the data flow are unproductive NULL waves patented und industrially used patented und industrially used NCL: A Brief Summary

29. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 29 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive recal l ARE THERE OTHER CODING OPTIONS?

30. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 30 (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Conditions for DI Coding

31. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 31 (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances Conditions for DI coding 0,0,0 ?

32. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 32 (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Conditions for DI coding

33. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 33 (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Conditions for DI coding 0,0,01,0,01,0,11,1,1 ?

34. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 34 (C1) Return to NULL forces separation between successive data waves (C1) Return to NULL forces separation between successive data waves (C2) Coding scheme guarantees direct switch from one legal value to next (only one rail changes!) (C2) Coding scheme guarantees direct switch from one legal value to next (only one rail changes!) Signal X X.a X.b X.bvalue 0 0NULL 0 1TRUE 1 0FALSE 1 1illegal What about NCL‘s Coding

35. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 35 ABY 000 010 100 111 0,1 1,0NULL & A B Y 00 NN N Synchronization of Waves no glitch! successive „0“s clearly separable

36. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 36 Transition Signaling Transition Signaling NULL-Convention Logic NULL-Convention Logic NCL vs. Trans. Signaling A0A0 A1A1 A=0A=1 A=0 A0A0 A1A1 A=1 A=0

37. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 37 More Efficient Coding? NCL employs a 4-phase (RTZ) version of transition signaling. NCL employs a 4-phase (RTZ) version of transition signaling. The „return to zero“ is due to the NULL waves. The „return to zero“ is due to the NULL waves. The NULL waves are unproductive and hence undesired. The NULL waves are unproductive and hence undesired. Can we employ 2-phase (NRZ) transition signaling instead? Can we employ 2-phase (NRZ) transition signaling instead?

38. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 38 Four-State Logic (FSL) Use 2 codes per logic value Use 2 codes per logic value X X.a X.b two-rail coding:

39. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 39 Alternate code sets („phase“) Alternate code sets („phase“) Completion detection: Check whether all bits belong to the same phase Completion detection: Check whether all bits belong to the same phase A H L H h l l h L L H H l l h hH t konsistent phase 0 consistent phase 1 NULL TRUE FALSE TRUE NULL TRUE FALSE TRUE FALSENULL NCL FSL FSL Flow Control

40. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 40 FSL AND-Gate: Truth Table YlhLH lll** hlh** L**LL H**LH IN_1 IN_2 * … hold last valid output

41. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 41 Four-State Logic (FSL)  An FSL gate holds its output until all inputs are in the same phase need storage capability (or feedback loop) even in combi- national gate Mem X1.a X1.b X1 X2.a X2.b X2 Y.a Y.b Y Mem

42. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 42 (C1) Phase change forces separation between successive data waves (C1) Phase change forces separation between successive data waves (C2) Coding scheme guarantees direct switch from one legal value in one phase to legal value in next phase (only one rail changes!) (C2) Coding scheme guarantees direct switch from one legal value in one phase to legal value in next phase (only one rail changes!) FSL and Code Conditions

43. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 43 A ABY 000 010 100 111 0,1 1,0 & A B Y 00 00 11 Synchronization of Waves no glitch! successive „0“s clearly separable

44. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 44 FSL retains all the charme of NCL FSL retains all the charme of NCL FSL provides double data throughput FSL provides double data throughput  implementation of 4-phase scheme tends to require more efforts (remains to be investigated) FSL: A Brief Summary

45. Evaluation of Properties Bounded Delay & Delay Insensitive Asynchronous Design Methods

46. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 46 Ideal Design Method An ideal design method … minimizes power consumption minimizes power consumption miminizes circuit overhead miminizes circuit overhead naturally supports composability naturally supports composability naturally aids testability naturally aids testability yields robust circuits yields robust circuits yields fast circuits. yields fast circuits. recal l

47. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 47 ! Area Efficiency BD area proportion devoted to intended logic function 0 (handshake logic negligible)

48. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 48 ! Area Efficiency NCL * [Smith & Ligthart ASP-DAC 2001] overheads for flow control (Micropipeline) flow control (Micropipeline) two-rail coding two-rail coding storage cells storage cells sum up to about 500% A F with standard cells 500% A F with standard cells 100%...200% A F with custom cells (*) 100%...200% A F with custom cells (*)

49. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 49 ! Area Efficiency FSL overheads similar to NCL but NULL state tends to result in more conveni- ent implementation than second phase rough estimation: 600% A F with standard cells 600% A F with standard cells 150%...250% A F with custom cells 150%...250% A F with custom cells

50. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 50 Area Efficiency - Comparison Area Efficiency sync.50% BD100% NCL50…33% FSL40…29%

51. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 51 Area Efficiency: Summary Asynchronous circuits save the need for the clock network, but require (relatively little) area for handshaking. Asynchronous circuits save the need for the clock network, but require (relatively little) area for handshaking. In addition DI circuits cause substantial circuit overheads for coding and completion detection. In addition DI circuits cause substantial circuit overheads for coding and completion detection. These overheads outweigh the savings for the clock tree, hence BD circuits promise the most area savings (the delay, however, is diffcult to implement) These overheads outweigh the savings for the clock tree, hence BD circuits promise the most area savings (the delay, however, is diffcult to implement)

52. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 52 ! Power Efficiency BD dissipated power (total) static part dynamic part assumption: handshaking increases dynamic power by 10% power for intended function circuit utilization

53. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 53 ! Power Efficiency NCL logic overhead (2.5) assumption: handshaking plus completion detection increase dyn. pwr by 10% coding overhead (2 trans/bit instead of 0.5 => 4x)

54. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 54 ! Power Efficiency FSL logic overhead (3) assumption: handshaking plus completion detection increase dyn. pwr by 10% coding overhead (1 trans/bit instead of 0.5 => 2x)

55. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 55 Pwr Efficiency - Comparison  =100%  =10%   0% sync.53%5.3% BD92%50% 10  NCL10%8% 4444 FSL16%11% 3.3 

56. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 56 Pwr Efficiency: Summary Asynchronous circuits save the power consumed by the clock network, and require less power for handshaking. Asynchronous circuits save the power consumed by the clock network, and require less power for handshaking. The DI circuits‘ additional transitions plus their substantial circuit overheads increase energy consumption. The DI circuits‘ additional transitions plus their substantial circuit overheads increase energy consumption. In summary the DI overheads outweigh the savings, hence BD methods are most effective for low-power applications. In summary the DI overheads outweigh the savings, hence BD methods are most effective for low-power applications.

57. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 57 ! Perform. Efficiency BD real computation time 2010050 10 3020 lib: worst vs. typcrosstalk, IR dropprocess variation clock skew unbalanced stages [Cortadella, ICCD’04]

58. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 58 ! Perform. Efficiency NCL no safety margins necessary no safety margins necessary but additional delay t dly for: ACK path (feedback required!) ACK path (feedback required!) completion detection completion detection additional circuit complexity additional circuit complexity and NULL waves halve throughput *[Cortadella, ICCD’04]

59. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 59 ! Perform. Efficiency FSL everything like in NCL everything like in NCLbut: double throughput double throughput *[Cortadella, ICCD’04]

60. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 60 Perf. Effic. - Comparison Perf. Efficiency sync.44% BD < 50% NCL FSL < 100%

61. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 61 ! Composability BD is similar to the synchronous case: Delays must be adjusted just like the clock BD is similar to the synchronous case: Delays must be adjusted just like the clock DI circuits work under all conditions, interface spec can be reduced to the function (plus handshake protocol). DI circuits work under all conditions, interface spec can be reduced to the function (plus handshake protocol). If a certain execution time/performance must be guaranteed, however, timing analysis is again necessary. BUT: If a certain execution time/performance must be guaranteed, however, timing analysis is again necessary. BUT: Even if the operation is too slow for any reason, the circuit will not fail to operate! Even if the operation is too slow for any reason, the circuit will not fail to operate! No metastability issues! Instead handshake required at all interfaces. No metastability issues! Instead handshake required at all interfaces.

62. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 62 How DI is DI? Basic cells are internally SDI (at best) Basic cells are internally SDI (at best) Obligatory feedback Obligatory feedback On module level DI is attainable, but On module level DI is attainable, but Inevitable (?) fork makes ACK path „unsafe“ Inevitable (?) fork makes ACK path „unsafe“ Reg design critical Reg design critical &

63. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 63 ! Robustness  All async techniques: timing is distributed, clock no more single point of failure timing is distributed, clock no more single point of failure  DI only: robust timing due to closed-loop control robust timing due to closed-loop control graceful degratation in case of violation graceful degratation in case of violation multi-rail coding of signals multi-rail coding of signals  complexity of interacting control loops  larger area

64. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 64 Syn versus FSL syn FSL Fault injection [Thesis Rahbaran]

65. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 65 ! Testability Scan chain is an extremely powerful concept; hard to beat Scan chain is an extremely powerful concept; hard to beat Asynchronous circuits (including BD) are said to be much harder to test Asynchronous circuits (including BD) are said to be much harder to test Only punctual concepts and ad-hoc solutions available Only punctual concepts and ad-hoc solutions available

66. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 66 Further Properties „Correctness by design“ (DI only) „Correctness by design“ (DI only) Beneficial EMR behavior Beneficial EMR behavior Conceptual elegance (DI only) Conceptual elegance (DI only) Readiness for future technologies (quantum, bio, optical, …) Readiness for future technologies (quantum, bio, optical, …)

67. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 67 need to determine clock period need to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent considerable design efforts, large design loops considerable design efforts, large design loops need to make worst-case assumptions need to make worst-case assumptions necessarily pessimistic necessarily pessimistic no robustness wrt. exceeding them no robustness wrt. exceeding them need to maintain global synchrony need to maintain global synchrony clock distribution problems clock distribution problems power consumption problems power consumption problems Gain of Delay Insensitive

68. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 68 Current status working 16-bit processor „ASPEAR“ (on FPGA platform) in FSL working 16-bit processor „ASPEAR“ (on FPGA platform) in FSL working design flow based on Synopsys working design flow based on Synopsys formal investigation of delay insensitivity (Modelchecking) formal investigation of delay insensitivity (Modelchecking) experimental comparison of robustness:SPEAR versus ASPEAR experimental comparison of robustness:SPEAR versus ASPEAR

69. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 69 Our visions autonomous sensor node autonomous sensor node no crystal oscillator no crystal oscillator UART-like communication UART-like communication low power (by diverse means) low power (by diverse means) high robustness (harsh environments) high robustness (harsh environments) develop „tailored“ lib cells / ASIC develop „tailored“ lib cells / ASIC delay insensitive memory delay insensitive memory (exp.) comparison with other approaches (exp.) comparison with other approaches

70. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 70 Conclusion for asyn: benefits for benefits for low activation Applications () low activation Applications () high robustness high robustness technologies with unknown timing technologies with unknown timing largely varying operatring conditions largely varying operatring conditions not good for not good for small feature sizes (static current!) small feature sizes (static current!) low area low area real-time real-time high speed (?) high speed (?)