1. Smart Dust Mote Core Architecture Brett Warneke, Sunil Bhave CS252 Spring 2000

2. Smart Dust Mote Core Architecture Smart Dust Overview Autonomous sensing and communications in 1 mm 3 Multiple sensors: temperature, light, vibration, etc. Batteries: 1 J/mm 3 Downlink:broadcast only Uplink: CCR draws 6.4pJ/bit

3. Smart Dust Mote Core Architecture System Diagram Core Transceiver back end Sensor Signal Processing Computation Memory Sensors Power Supply Receiver Front End ADC Real Time Clock CCR Driver

4. Smart Dust Mote Core Architecture Design Goals Minimize energy through architecture –Minimum energy  ASIC implementation Dynamic reconfigurability –How much is necessary  tradeoff with ASIC mapping –Energy driven operation modes Military base monitoring –Typical application scenario to guide design –Detect heat and vibration of vehicles –Real time sensor readings –Logged sensor readings ASICMicroprocessor

5. Smart Dust Mote Core Architecture Desired Operations Immediate –Transmit ID  Mote health report –Transmit current readings from one/all sensors –Send logged data for sensor X –Calibrate real-time clock Reconfiguration – Start logging data from sensor X sampled every T seconds – Set logging threshold and filter coefficients – Set ‘ScatterCast’ interval to T seconds – Set your wakeup interval to T seconds

6. Smart Dust Mote Core Architecture One Approach: ‘Golden Processor’

7. Smart Dust Mote Core Architecture Golden Processor: Features Laser Reprogrammable Gated clocks everywhere Processor stall mode Eight execution phases –1 cpi including fetch –No pipelining to reduce overhead –Forced sequencing Minimize glitching Prevent bus conflicts and thus short circuit current –Robust to delay variations from process spreads, voltage swings (will test from 0.3V to 1.4V), and temperature

8. Smart Dust Mote Core Architecture New Approach: Top-Level Diagram Sensors Power Supply Receiver Front End ADC Real Time Clock CCR Driver Timer Bank Setup Memroy Reconfigurable Datapath Components SRAM

9. Smart Dust Mote Core Architecture All activity initiated by timers –When timer expires, Setup Memory 1 configures the datapath –Additional setup memories can be invoked to perform more steps Two rates available for each timer –Two sensor sampling rates for normal polling and interesting events –Delay receiver for a long period before returning to normal rate Multiple setup memory banks for energy- driven operation  modes Timers and Setup Memory Timer value 1Timer value 2TimerSetup Mem 1Setup Mem 2

10. Smart Dust Mote Core Architecture Reconfigurable Datapath Components Adder Timing Recovery Mote ID Mem Data Addr Reg Sensor Reg n Comparator Threshold Mem n Packet Decoder Config Mem FFT Config Mem FIR Filter Data Recovery Packet Encoder CRCFIFO Immediate Mode Setup Reg Immediate mode packets load Immediate Mode Setup Register to configure the datapath Data-driven components Wiring options –many point-to-point control and data wires –wire mesh with switches for routing Global Setup Reg

11. Smart Dust Mote Core Architecture Example Configuration: Sensor Logging Timer value 1 Timer value 2 Timer Setup Mem 1 Setup Mem 2 Adder Data Addr Reg Sensor Reg Comparator Threshold Mem Sensor ADC SRAM PWR Done Data Done Data PWR Addr Data Zero WE True False Done Open control signals are driven by the setup memory 543210 Zero Setup Mem 1 Open control signals are driven by the setup memory Sensor Reg Sensor ADC PWR Done Data PWR Done Data Adder Threshold Mem Done Data PWR Done Data PWR Comparator False True Data Addr Reg SRAM PWR Addr Data WE Done Setup Mem 2 Open control signals are driven by the setup memory

12. Smart Dust Mote Core Architecture Comparison of Three Architectures ARM8 estimations from Peggy Laramie, M.S. thesis 1998 –energy is for a set of instructions equivalent to the configuration on the previous slide –Vdd=1V (scaled from the reported numbers) Energy estimations for other approaches were to be from Powermill

13. Smart Dust Mote Core Architecture Conclusions Smart Dust needs minimum energy controller New non-microprocessor architecture designed –Timer controlled –Reconfigurable datapath –Should be much lower energy than a microprocessor architecture, but unconfirmed