1. TK 2123 COMPUTER ORGANISATION & ARCHITECTURE
Lecture 5: CPU and Memory

2. Contents This lecture will discuss: Computer Systems Organisation.
Instruction Execution.
Design Principles for Modern Computers.
Prepared by: Dr Masri Ayob - TK2123

3. Program Concept Hardwired systems are inflexible
General purpose hardware can do different tasks, given correct control signals
Instead of re-wiring, supply a new set of control signals
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4. What is a program? A sequence of steps
For each step, an arithmetic or logical operation is done
For each operation, a different set of control signals is needed
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5. Function of Control Unit
For each operation a unique code is provided
e.g. ADD, MOVE
A hardware segment accepts the code and issues the control signals
We have a computer!
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6. Components of Computer
Central Processing Unit (CPU) has:
The Control Unit (CU)
the Arithmetic and Logic Unit (ALU).
Data and instructions need to get into the system and results out
Input/output
Temporary storage of code, data and results is needed
Main memory
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7. Central Processing Unit
The organisation of a simple computer with one CPU and two I/O devices
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8. The data path of a typical Von Neumann machine.
CPU Organization
The data path of a typical Von Neumann machine.
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9. Components of the CPU
The arithmetic/logic unit is the component of the CPU where data is held temporarily and where calculations take place.
The control unit controls and interprets the execution of instructions .
The control unit determines the particular instruction to be executed by reading the contents of a program counter (PC), sometimes called an instruction pointer, which is a part of the control unit.
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10. Components of the CPU
Normally, instructions are executed sequentially.
The sequence of instructions is modified by executing instructions that change the contents of the program counter.
A Memory Management Unit within the control unit supervises the fetching of instructions and data from memory.
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11. The Concept Of Registers
A register is a single, permanent storage location within the CPU used for a particular, defined purpose.
A register is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations.
Each register is wired within the CPU to perform its specific role.
each register serves a particular purpose.
The register’s size, the way it is wired, and even the operations that take place in the register reflect the specific function that the register performs in the computer.
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12. The Concept Of Registers
They are not addressed as a memory location, but instead are manipulated directly by the control unit during the execution of instructions.
They may be as small as a single bit or as wide as several bytes, ranging usually from one to 128 bits.
A register may hold:
data being processed,
an instruction being executed,
a memory or I/O address to be accessed,
or even special binary codes used for some other purpose.
Some registers serve many different purposes, while others are designed to perform a single, specialised task.
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13. The Concept Of Registers
Registers are basic working components of the CPU.
The control unit contains several important registers:
the program counter (PC) register holds the address of the current instruction being executed.
The instruction register (IR) holds the actual instruction being executed currently by the computer.
The memory address register (MAR) holds the address of a memory location.
The memory data register (MDR), sometimes known as the memory buffer register, will hold a data value that is being stored to or retrieved from the memory location currently addressed by the memory address register.
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14. The Concept Of Registers
The CU also contain several 1-bit registers, sometimes known as flags, that are used to allow the computer to keep track of special conditions such as:
arithmetic carry and overflow,
power failure, and internal computer error.
Usually, several flags are grouped into one or more status registers.
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15. The Concept Of Registers
Most registers support four primary types of operations:
Registers can be loaded with values from other locations, in particular from other registers or from memory locations.
Data from another location can be added to or subtracted from the value previously stored in a register, leaving the sum or difference in the register.
Data in a register can be shifted or rotated right or left by one or more bits.
The value of data in a register can be tested for certain conditions, such as zero, positive, negative, or too large to fit in the register.
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16. THE MEMORY UNIT
The memory address register (MAR) and the memory data register (MDR), act is an interface between the CPU and memory.
The MDR is called the memory buffer register by some computer manufacturers.
Each cell in the memory unit holds one bit of data.
The cells are organized in rows.
Each row consists of a group of one or more bytes.
In modern computers, it is common to address eight bytes at a time to speed up memory access between the CPU and memory.
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18. THE MEMORY UNIT
The MAR holds the address in the memory that is to be “opened” for data.
The MAR is connected to a decoder that interprets the address and activates a single address line into the memory.
The MDR is designed such that it is effectively connected to every cell in the memory unit.
Each bit of the MDR is connected in a column to the corresponding bit of every location in memory.
The addressing method assures that only a single row of cells is activated at any given time.
Only one memory location is addressed at any one time.
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20. Memory Capacity
The number of bits in the MAR determines how many different address locations can be decoded.
For a MAR of width k bits, the number of possible memory addresses is
M = 2k
For example: A 32-bit memory address allows a memory capacity of 4 gigabytes (GB)
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21. Memory Capacity
The size of the word to be retrieved or stored in a single operation is determined by the size of the MDR and by the width of the bus connecting memory to the CPU.
In most modern computers, data and instructions found in memory are addressed in multiples of 8-bit bytes.
the MDR is usually designed to retrieve the data or instruction(s) from a sequence of several successive addresses all at once, and the MDR will be several bytes wide.
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22. Instruction Cycle Two steps: Fetch Execute
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23. Fetch/Execute Cycle Execute the instruction.
Program Counter (PC) holds address of next instruction to fetch
Processor fetches instruction from memory location pointed to by PC
Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs required actions.
If instructions uses word in memory, fetch the word into CPU register.
Execute the instruction.
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24. Execute Cycle Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
e.g. jump
Combination of above
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25. Design Principles for Modern Computers
All instructions directly executed by hardware
Maximise rate at which instructions are issued
Instructions should be easy to decode
Only loads, stores should reference memory
Provide plenty of registers
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26. Instruction-Level Parallelism
A five-stage pipeline
The state of each stage as a function of time. Nine clock cycles are illustrated
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27. Superscalar Architectures (1)
Dual five-stage pipelines with a common instruction fetch unit.
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28. Superscalar Architectures (2)
A superscalar processor with five functional units.
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29. Processor-Level Parallelism (1)
An array of processor of the ILLIAC IV type.
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30. Processor-Level Parallelism (2)
A single-bus multiprocessor.
A multicomputer with local memories.
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31. Primary Memory: Memory Addresses (1)
Three ways of organizing a 96-bit memory.
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32. Primary Memory : Memory Addresses (2)
Number of bits per cell for some historically interesting commercial computers
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33. Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. memory parity error
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34. Program Flow Control
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35. Interrupt Cycle Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted program
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36. Transfer of Control via Interrupts
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37. Instruction Cycle with Interrupts
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38. Program Timing Short I/O Wait
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39. Program Timing Long I/O Wait
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40. Multiple Interrupts Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns to previous interrupt
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41. Multiple Interrupts - Sequential
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42. Multiple Interrupts – Nested
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43. Time Sequence of Multiple Interrupts
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44. Connecting All the units must be connected
Different type of connection for different type of unit
Memory
Input/Output
CPU
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45. Computer Modules
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46. Memory Connection Receives and sends data
Receives addresses (of locations)
Receives control signals
Read
Write
Timing
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47. Input/Output Connection(1)
Similar to memory from computer’s viewpoint
Output
Receive data from computer
Send data to peripheral
Input
Receive data from peripheral
Send data to computer
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48. Input/Output Connection(2)
Receive control signals from computer
Send control signals to peripherals
e.g. spin disk
Receive addresses from computer
e.g. port number to identify peripheral
Send interrupt signals (control)
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49. CPU Connection Reads instruction and data
Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts
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50. Buses There are a number of possible interconnection systems
Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
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51. What is a Bus? A communication pathway connecting two or more devices
Usually broadcast
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown
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52. Data Bus Carries data Width is a key determinant of performance
Remember that there is no difference between “data” and “instruction” at this level
Width is a key determinant of performance
8, 16, 32, 64 bit
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53. Address bus Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
Bus width determines maximum memory capacity of system
e.g has 16 bit address bus giving 64k address space
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54. Control Bus Control and timing information Memory read/write signal
Interrupt request
Clock signals
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55. Bus Interconnection Scheme
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56. Big and Yellow? What do buses look like?
Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
e.g. PCI
Sets of wires
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57. Physical Realization of Bus Architecture
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58. Single Bus Problems Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems
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59. Traditional (ISA) (with cache)
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60. High Performance Bus
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61. Bus Types Dedicated Multiplexed Separate data & address lines
Shared lines
Address valid or data valid control line
Advantage - fewer lines
Disadvantages
More complex control
Ultimate performance
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62. Bus Arbitration More than one module controlling the bus
e.g. CPU and DMA controller
Only one module may control bus at one time
Arbitration may be centralised or distributed
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63. Centralised or Distributed Arbitration
Single hardware device controlling bus access
Bus Controller
Arbiter
May be part of CPU or separate
Distributed
Each module may claim the bus
Control logic on all modules
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64. Timing Co-ordination of events on bus Synchronous
Events determined by clock signals
Control Bus includes clock line
A single 1-0 is a bus cycle
All devices can read clock line
Usually sync on leading edge
Usually a single cycle for an event
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65. Synchronous Timing Diagram
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66. Asynchronous Timing – Read Diagram
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67. Asynchronous Timing – Write Diagram
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68. PCI Bus Peripheral Component Interconnection
Intel released to public domain
32 or 64 bit
50 lines
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69. PCI Bus Lines (required)
Systems lines
Including clock and reset
Address & Data
32 time mux lines for address/data
Interrupt & validate lines
Interface Control
Arbitration
Not shared
Direct connection to PCI bus arbiter
Error lines
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70. PCI Bus Lines (Optional)
Interrupt lines
Not shared
Cache support
64-bit Bus Extension
Additional 32 lines
Time multiplexed
2 lines to enable devices to agree to use 64-bit transfer
JTAG/Boundary Scan
For testing procedures
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71. PCI Commands Transaction between initiator (master) and target
Master claims bus
Determine type of transaction
e.g. I/O read/write
Address phase
One or more data phases
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72. Thank you Q & A
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