1. San Jose State University Electrical Engineering EE-166 4 Bit Serial to Parallel Converter Prof. David Parent, PhD Members: Quang Ly Derek Kwong Hector Vidal

2. San Jose State University Electrical Engineering Specifications: Clock f = 25 MHz, duty cycle = 50% Conversion every 4 clock cycles Output C load = 10 pF Power < 500 mW

3. San Jose State University Electrical Engineering Block Diagram:

4. San Jose State University Electrical Engineering D Flip-Flop with Reset Schematic:

5. San Jose State University Electrical Engineering Counter Schematic:

6. San Jose State University Electrical Engineering Serial to Parallel Schematic:

7. San Jose State University Electrical Engineering Output Buffer Schematic:

8. San Jose State University Electrical Engineering 4bit Serial to Parallel Test Bench Schematic:

9. San Jose State University Electrical Engineering Simulation waveforms:

11. San Jose State University Electrical Engineering Simulation waveforms (Reset):

12. San Jose State University Electrical Engineering Super Buffer Design: Stage 1: Wp=250.4  m, Wn= 90  m Stage 2: Wp= 89.2  m, Wn= 32  m Stage 3: Wp= 32  m, Wn= 11.6  m Stage 4: Wp= 11.6  m, Wn= 4  m 

13. San Jose State University Electrical Engineering 4bit Serial to Parallel Circuit Layout:

14. San Jose State University Electrical Engineering Counter Layout:

15. San Jose State University Electrical Engineering D Flip-Flop Layout:

16. San Jose State University Electrical Engineering Output Buffer Layout:

17. San Jose State University Electrical Engineering Serial to Parallel Layout:

18. San Jose State University Electrical Engineering Final Product:

19. San Jose State University Electrical Engineering Super Buffer Layout:

20. San Jose State University Electrical Engineering Test results: Rise time (t r ) = 3.9 ns Fall time (t f ) = 4.05 ns Total area = 22.5 mil 2 Power < 350 mW Peak current = 16.6 mA