1. CS 150 - Fall 2007 – Lec. #23: Testing - 1 Testing Methodologies Sarah Bird *Many Slides from Randy Katz from Spring 2007 and Kurt Keuzter from Fall 2007

2. CS 150 - Fall 2007 – Lec. #23: Testing - 2 zStart with Some Specification yThis Class: xLab Write Ups yIndustry: xContract Restrictions xHigh and Low-Level Specifications from Architects and Designers zConvert the Design to HDL yThis Class: xYou design Microarchitecture xWrite Verilog using components provided by the TA’s or the Standard Library and also from scratch yIndustry: xVerilog or VHDL using standard components or previous designs Specification Design Process Netlist HDL Netlist Layout Final Product Manual Design and Coding RTL Synthesis Logic Optimization Physical Design Implemetation

3. CS 150 - Fall 2007 – Lec. #23: Testing - 3 zConvert HDL into RTL and Optimize Design yThis Class: xSynplify Pro yIndustry: xOther Synthesis tools x2 & Multi-Level Logic Optimization zConvert the Netlist into a Layout yThis Class: xXilinx Map & PAR yIndustry: xPlace and Route Tools xTechnology Mapping zConvert Layout to Final Product yThis Class: xDownload to Board..Configure FPGA yIndustry: xSend Layout to Fab xMake Masks xManufacture Chips Specification Design Process Netlist HDL Netlist Layout Final Product Manual Design and Coding RTL Synthesis Logic Optimization Physical Design Implemetation

4. CS 150 - Fall 2007 – Lec. #23: Testing - 4 Testing zHow do I know what that what I designed is really what I got back??? ySpecification to HDL xVerification Formal Verification Simulation - such as Model Sim yHDL to Layout xEquivlance testing xTool Verification

5. CS 150 - Fall 2007 – Lec. #23: Testing - 5 Why Manufacture Test? zHow do I know that what I designed is really what I got back??? zIn CS150, we (mostly) trust the FPGA board to work correctly once the design is downloaded. zHowever can we trust that the hardware chip we get will work?

6. CS 150 - Fall 2007 – Lec. #23: Testing - 6 Why Manufacture Test?  Manufacturing defects can manifest in a variety of ways:  Bridging  Contaminants  Shorts  Opens yTransistors stuck-open  These need to be reduced to models:  Single stuck-at-1, stuck-at-0  Multiple stuck-at-1, stuck-at-0  Delay fault models: ･ Gate ･ Path  single-stuck-at fault model ubiquitous  some use of delay fault modeling

7. CS 150 - Fall 2007 – Lec. #23: Testing - 7 Testing of Logic Circuits zFault Models zTest Generation and Coverage zFault Detection zDesign for Test

8. CS 150 - Fall 2007 – Lec. #23: Testing - 8 Fault Model zStuck-At Model yAssume selected wires (gate input or output) are “stuck at” logic value 0 or 1 yModels certain kinds of fabrication flaws that short circuit wires to ground or power, or broken wires that are floating xWire w stuck-at-0: w/0 xWire w stuck-at-1: w/1 yOften assume there is only one fault at a time—even though in real circuits multiple simultaneous faults are possible and can mask each other yObviously a very simplistic model!

9. CS 150 - Fall 2007 – Lec. #23: Testing - 9 Fault Model zSimple example: zGenerate a test case to determine if a is stuck at 1 yTry 000 yIf a stuck at 1, expect to see f = 0, but see 1 instead w1w2w3w1w2w3 a/1 b c d f 000000 0 see 1 but should be 0

10. CS 150 - Fall 2007 – Lec. #23: Testing - 10 Fault Model zSimple example w1w2w3w1w2w3 abcabc d f Test w1 w2 w3 000 001 010 011 100 101 110 111 a/0 X X X a/1 X X X b/0 X b/1 X c/0 X c/1 X d/0 X d/1 XX f/0 X X X X X f/1 X X X Fault Detected Test Set

11. CS 150 - Fall 2007 – Lec. #23: Testing - 11 Problems with Fault Model zIn general, n-input circuits require much less than 2 n test inputs to cover all possible stuck-at-faults in the circuit zHowever, this number is usually still too large in real circuits for practical purposes zFinding minimum test cover is an NP-hard problem too

12. CS 150 - Fall 2007 – Lec. #23: Testing - 12 Path Sensitization zWire-at-time testing too laborious zBetter to focus on wiring paths, enabling multi-wire testing at the same time z“Activate” a path so that changes in signal propagating along the path affects the output

13. CS 150 - Fall 2007 – Lec. #23: Testing - 13 Path Sensitization zSimple Example: To activate the path, set inputs so that w 1 can influence f E.g., w 2 = 1, w 3 = 0, w 4 = 1 AND gates: one input at 1 passes the other input NOR gates: one input at 0 inverts the other input To test: w 1 set to 1 should generate f = 0 if path ok faults a/0, b/0, c/1 cause f = 1 w 1 set to 0 should generate f = 1 if path ok faults a/1, b/1, c/0 cause f = 0 One test can capture several faults at once! w1w2w1w2 b f c a w3w3 w4w4 1 0 1

14. CS 150 - Fall 2007 – Lec. #23: Testing - 14 Path Sensitization zGood news: one test checks for several faults yNumber of paths much smaller than number of wires yStill an impractically large number of paths for large-scale circuits zPath idea can be used to “propagate” a fault to the output to observe the fault ySet inputs and intermediate values so as to pass an internal wire to the output while setting inputs to drive that internal wire to a known value yIf propagated value isn’t as expected, then we have found a fault on the isolated wire

15. CS 150 - Fall 2007 – Lec. #23: Testing - 15 Fault Propagation w1w2w1w2 b f c g w3w4w3w4 h k w1w2w1w2 f w3w4w3w4 b/0 0 1 1 1111 D D 0000 D

16. CS 150 - Fall 2007 – Lec. #23: Testing - 16 Fault Propagation w1w2w1w2 b f c g w3w4w3w4 h k w1w2w1w2 f D w3w4w3w4 g/1 1 1 0000 0000 D D D

17. CS 150 - Fall 2007 – Lec. #23: Testing - 17 Tree Structured Circuits z To test inputs stuck-at-0 at given AND gate ySet inputs at other gates to generate AND output of zero yForce inputs at selected gate to generate a one yIf f is 1 then circuit ok, else fault z To test inputs stuck-at-1 at given AND gate yDrive input to test to 0, rest of inputs driven to 1 yOther gates driven with inputs that force gates to 0 yIf f is 0 then fault, else OK w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f

18. CS 150 - Fall 2007 – Lec. #23: Testing - 18 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 111010000111010000 000000 Stuck-at-0 0

19. CS 150 - Fall 2007 – Lec. #23: Testing - 19 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 010111110010111110 000000 Stuck-at-0 0

20. CS 150 - Fall 2007 – Lec. #23: Testing - 20 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 000101111000101111 000000 Stuck-at-0 0

21. CS 150 - Fall 2007 – Lec. #23: Testing - 21 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 011110110011110110 100100 Stuck-at-1 1

22. CS 150 - Fall 2007 – Lec. #23: Testing - 22 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 011110110011110110 010010 Stuck-at-1 1

23. CS 150 - Fall 2007 – Lec. #23: Testing - 23 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 011110110011110110 001001 Stuck-at-1 1

24. CS 150 - Fall 2007 – Lec. #23: Testing - 24 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 101100011101100011 100100 Stuck-at-1 1

25. CS 150 - Fall 2007 – Lec. #23: Testing - 25 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 101100011101100011 001001 Stuck-at-1 1

26. CS 150 - Fall 2007 – Lec. #23: Testing - 26 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 110011000110011000 010010 Stuck-at-1 1 Any other stuck-at-1 cases covered?

27. CS 150 - Fall 2007 – Lec. #23: Testing - 27 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 100101011100101011 010010 Stuck-at-1 1 Any other stuck-at-1 cases covered? Was that case already covered?

28. CS 150 - Fall 2007 – Lec. #23: Testing - 28 Tree Structured Circuits w1w3w4w1w3w4 w2w3w4w2w3w4 w1w2w3w1w2w3 f 1234567812345678 w110001110w110001110 w311010100w311010100 w410011000w410011000 w201111010w201111010 w311010100w311010100 w401100111w401100111 w101110001w101110001 w201111010w201111010 w300101011w300101011 w110001110w110001110 w201111010w201111010 w300101011w300101011 w401100111w401100111 Stuck-at-0 Stuck-at-1 Product Term Test 000001101000001101 001001 Stuck-at-1 1 All inputs stuck-at-1’s covered now

29. CS 150 - Fall 2007 – Lec. #23: Testing - 29 Random Testing zSo far: deterministic testing zAlternative: random testing yGenerate random input patterns to distinguish between the correct function and the faulty function Number of Tests Probability Fault Detected Small number of tests has reasonable probability of finding the fault

30. CS 150 - Fall 2007 – Lec. #23: Testing - 30 Announcements TA’s are not holding labs next week. Check the Website for posted office hours.

31. CS 150 - Fall 2007 – Lec. #23: Testing - 31 Sequential Testing zDue to embedded state inside flip-flops, it is difficult to employ the same methods as with combinational logic zAlternative approach: design for test yScan Path technique: FF inputs pass through multiplexer stages to allow them to be used in normal mode as well as a special test shift register mode

32. CS 150 - Fall 2007 – Lec. #23: Testing - 32 Scan Path Technique z Configure FFs into shift register mode (red path) z Scan in test pattern of 0s and 1s z Non-state inputs can also be on the scan path (think synchronous Mealy Machine) z Run system for one clock cycle in “normal” mode (black path)— next state captured in scan path z Return to shift register mode and shift out the captured state and outputs Combinational Logic

33. CS 150 - Fall 2007 – Lec. #23: Testing - 33 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs z Y1Y2Y1Y2 D Q Q 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 0 D Q Q

34. CS 150 - Fall 2007 – Lec. #23: Testing - 34 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 1 0 0 D Q Q D Q Q

35. CS 150 - Fall 2007 – Lec. #23: Testing - 35 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 1 0 1 0 D Q Q D Q Q

36. CS 150 - Fall 2007 – Lec. #23: Testing - 36 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs yNormal w=0 z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 1 0 1 0 0 D Q Q D Q Q

37. CS 150 - Fall 2007 – Lec. #23: Testing - 37 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs yNormal w=0 yOutput z=0, Y1=0, Y2=0 z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 1 0 0 0 0 0 D Q Q D Q Q

38. CS 150 - Fall 2007 – Lec. #23: Testing - 38 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs yNormal w=0 yOutput z=0, Y1=0, Y2=0 yObserve z directly z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 0 0 0 0 0 0 D Q Q D Q Q

39. CS 150 - Fall 2007 – Lec. #23: Testing - 39 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs yNormal w=0 yOutput z=0, Y1=0, Y2=0 yObserve z directly yScan out Y1, Y2 z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 0 0 0 0 D Q Q D Q Q

40. CS 150 - Fall 2007 – Lec. #23: Testing - 40 Scan Path Example zw,y1,y2 test vector 001 yScan 01 into y1, y2 FFs yNormal w=0 yOutput z=0, Y1=0, Y2=0 yObserve z directly yScan out Y1, Y2 z Y1Y2Y1Y2 0 1 0 1 y1y2y1y2 w Scan-in Scan-out G/S 0 0 0 D Q Q D Q Q

41. CS 150 - Fall 2007 – Lec. #23: Testing - 41 Built-in Self-Test (BIST) zTest Vector Generator yPseudorandom tests with a feedback shift register ySeed generates a sequence of test patterns yOutputs combined using the same technique yGenerates a unique signature that can be checked to determine if the circuit is correct Test Vector Generator Circuit Under Test Response Compressor x 0. x n-1 P 0. P m-1 Signature

42. CS 150 - Fall 2007 – Lec. #23: Testing - 42 Many Types of BIST Engines-Examples zArray BIST yTests the memory arrays yUsually writes a series of patterns to the array and checks for errors yMay include Array Repair for a small number of errors zLogic BIST yRun patterns through large areas of logic zPhysical BIST yTest the physical interface…connections to off chip

43. CS 150 - Fall 2007 – Lec. #23: Testing - 43 Linear Feedback Shift Register D Q Q D Q Q D Q Q D Q Q D Q Q D Q Q D Q Q D Q Q P Signature Random Test Pattern Input from circuit under test

44. CS 150 - Fall 2007 – Lec. #23: Testing - 44 Linear Feedback Shift Register zStarting with the pattern 1000, generates 15 different patterns in sequence and then repeats zPattern 0000 is a no-no D Q Q D Q Q D Q Q D Q Q x3x3 x2x2 x1x1 x0x0 x3x2x1x0fx3x2x1x0f f 1000110001 1100111001 1110111101 1111011110 0111101111 1011010110 0101101011 1010110101 1101011010 0110001100 0011100111 1001010010 0100001000 0010000100 0001100011 1000110001 … … Initial Configuration

45. CS 150 - Fall 2007 – Lec. #23: Testing - 45 Linear Feedback Shift Register zMulti-input Compressor D Q Q D Q Q P3P3 P2P2 D Q Q P1P1 D Q Q P0P0 Signature Circuit Under Test Outputs

46. CS 150 - Fall 2007 – Lec. #23: Testing - 46 Complete Self-Test System Combinational Circuit FFs and Muxes MIC SIC Scan out PRBSG Scan in MUXMUX PRBSG Normal Inputs Random Test Sequences Multi-input Compressor Random Test Sequences Single-input Compressor Pseudo Random Binary Sequence Generator

47. CS 150 - Fall 2007 – Lec. #23: Testing - 47 Putting it all Together zFault Models are used to generate interesting input vectors and their corresponding output vectors zA subset of these vectors are selected to make a sufficiently short sequence of tests with a reasonable amount of coverage zVectors are combined to together to create scan patterns that test for faults by using shift register tests or using the BIST engine. zAt the Fab the sequence of test patterns are run on every wafer using a tester to sort the good chips from the bad chips. zAfter packaging the chip another (similar) set of test is run on the packaged chip.

48. CS 150 - Fall 2007 – Lec. #23: Testing - 48 Current Status on Manufacture Test zPractical approach to test: use scan -achieve 99%+ stuck-at coverage zSingle stuck-at-fault testing for combinational logic is a “solved problem” yDespite the fact that it is NP-complete yAfter 20+ years of research yResults applied to combinational-equivalence checking zSingle stuck-at-fault testing for sequential circuits is an intractable problem yTime-frame expansion used in state-space search zPrincipal research focus is on ATPG for enhanced fault models yDelay fault testing zOther approaches yBIST

49. CS 150 - Fall 2007 – Lec. #23: Testing - 49 Bring-Up zWhat if my error isn’t due to a physical defect?

50. CS 150 - Fall 2007 – Lec. #23: Testing - 50 Summary zMuch of the chip design schedule is dominated by testing (as much as 2/3!). zWe need to test our design at every step of the process zManufacturing Test yFault models xApproach for determining how to develop a test pattern sequence xWeakness is the single fault assumption yScan Path xTechnique for applying test inputs deep within the system, usually for asserting state xTechnique for getting internal state to edges of circuit for observation yBuilt-in Test xFounded on the approach of random testing xGenerate pseudo random sequences; compute signature; determine if signature generated is same as signature of a correctly working circuity