1. Counters Mano & Kime Sections 5-4, 5-5

2. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

3. Counters ---

4. A 4-bit Ripple Counter Recall... Less Significant Bit output is Clock for Next Significant Bit! (Clock - active low)

5. J-K Flip-Flop from a D Flip-Flop D Q = J & !Q # !K & Q D Q = Q D Q = 0 D Q =!Q # Q = 1 D Q = !Q

10. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

11. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter

12. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

13. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

14. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0

15. CUPL Simulation Output File

16. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D 3-Bit Down Counter

17. Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

18. 3-Bit Down Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

19. 3-Bit Down Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

20. Up-Down Counter Up-Down Counter Q0 Q1 Q2 clock UD UD = 0: count up UD = 1: count down

21. Up-Down Counter 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 UD Q2 Q1 Q0 Q2.D Q1.D Q0.D 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 UD Q2 Q1 Q0 Q2.D Q1.D Q0.D Up-CounterDown-Counter

22. UD Q2 Q1 Q0 00011110 00 01 11 10 Up-Down Counter Make Karnaugh maps for Q2.D, Q1.D, and Q0.D

23. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

24. J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

25. J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

26. J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

27. J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

28. 4 - Bit Counter Logic Diagram

29. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

31. 4-Bit Binary Counter with Reset