1. Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

2. The Shifter 3 clock cycles will be needed if using a bidirectional shift register with parallel load.  A clock pulse loads the output of Bus B into the shift register.  Another clock pulse performs the shift.  Another clock pulse transfer the result to the destination register.

3. A Faster Approach: Combinational Shifters Input I R : right shift, I L : left shift. Output R: right shift, L: left shift. B 3 I R I L S Serial output L Serial output R 2 B 2 B 1 B 0 H 0 H 1 H 2 H 3 S M U X 012 S M U X 012 S M U X 012 S M U X 012

4. 4-Bit Barrel Shifter Depending on S, the barrel shifter can shift or rotate the input data by several bits. D 3 S 0 3S 1 S 0 M U X D 2 D 1 D 0 Y 0 Y 1 Y 2 Y 3 S 1 0123S 1 S 0 M U X 0123S 1 S 0 M U X 0123S 1 S 0 M U X 012

5. Function Table for 4-Bit Barrel Shifter

6. Datapath Representation Reduce the apparent complexity of the datapath with a hierarchical structure. The registers, and the multiplexer, decoder, and enable hardware for accessing them are encapsulated into a register file. The ALU, shifter, Mux F and status bits are encapsulated into a function unit. The details of the register file and the function unit are now at a lower design hierarchy. Address out Data out Constant in MB select Bus A Bus B FS V C N Z MD select n D data Write D address A addressB address A dataB data 2 m x n Register file m m m n n n n n AB Function unit F 4 MUX B 10 MUX D 01 n n Data in

8. Register File A set of registers having common micro-operations performed on them may be organized into a register file. The typical register file is a special type of fast memory that permits one or more words to be read or written, all simultaneously.

9. G Select, H Select, and MF Select Codes Defined in Terms of FS

10. The Control Word There are 16 binary control inputs to the datapath. Their combined values specify a control word. Recall that  DA: destination register address.  AA and BA: the addresses of A and B operands.  MB and MD: selects muxes B and D respectively.  FS : function select for the function unit.  RW : write to the register file. Control word DAAABA M B FS M D R W 1514131211109876543210

11. Block Diagram

12. Examples of Microoperations for the Datapath: Symbolic Representation Micro- operationDAAABAMBFSMDRW R1R2R3RegisterFunctionWrite R4—R6RegisterFunctionWrite R7R7—RegisterFunctionWrite R1R0—ConstantFunctionWrite ——R3Register——No Write R4————Data inWrite R5R0R0RegisterFunctionWrite R1R2R3 –  F AB1 + = R4sl R6  FslB = R7R7 1 +  F A1 += R1R0 2 +  F AB += Data outR3  R4Data in  R5 0  F AB  =

13. Examples of Microoperations for the Datapath: Binary Representation

14. Simulation of the Microoperation Sequence

15. A Simple Computer Architecture Instruction Set Architecture: defines the boundary between hardware and software. An instruction is a collection of bits that instructs the computer to perform a specific operation. We call the collection of instructions for a computer its instruction set and a thorough description of the instruction set its instruction set architecture(ISA).

16. Storage Resources The following diagram depicts the computer structure as viewed by a user programming it in a language that directly specifies the instructions to be executed. Instruction memory 2 15 x 16 Data memory 2 15 x 16 Register file 8 x 16 Program counter (PC)

17. Three Instruction Formats An instruction consists of an operation code, several fields about the operands, and possibly a field about the location to store the result. (c) Jump and Branch (a) Register Opcode Destination register (DR) Source reg- ister A (SA) Source reg- ister B (SB) 159865320 (b) Immediate Opcode Destination register (DR) Source reg- ister A (SA) 159865320 Operand (OP) Opcode Source reg- ister A (SA) 159865320 Address (AD) (Right) Address (AD) (Left)

18. Register Instructions SA: Source Register A, SB: Source Register B, DR: Destination Register. Consider the instruction R1 <- R2 + R3. Here SA=R2, SB=R3, DR=R1. (a) Register Opcode Destination register (DR) Source reg- ister A (SA) Source reg- ister B (SB) 159865320

19. Immediate Instructions SA: source register A, DR: Destination register OP: an immediate number. Consider the instruction R0 <- R1 + 3. Here SA = R1, OP = 3, DR = R1. (b) Immediate Opcode Destination register (DR) Source reg- ister A (SA) 159865320 Operand (OP)

20. Jump and Branch Instructions SA : source register A. AD left + AD right : a number with signed 2s complement representation. Consider the instruction 1100000 101 110 100. Here SA=R6, AD=-20. It is equivalent to “If R6=0, PC<-PC-20.” (c) Jump and Branch Opcode Source reg- ister A (SA) 159865320 Address (AD) (Right) Address (AD) (Left)

21. Instruction Specifications for the Simple Computer

22. Memory Representation of Instructions and Data

23. Block Diagram for a Single-Cycle Computer

24. Control Unit of the Single Cycle Simple Computer We have described the design of its datapath. The block diagram for this computer has a hardwired control unit that fetches and executes an instruction in a single clock cycle. We do not write to the instruction memory, making it appear in this model to be a combinational rather than a sequential component.

25. The Program Counter (PC) The PC provides the instruction address to the instruction memory. The PC is updated in each clock cycle. The behaviour of the PC is determined by the opcode, N, and Z. PC OperationPLJBBC Count Up0XX Jump11X Branch on Negative (else Count Up)101 Branch on Zero (else Count Up)100

26. THANKS!