1. ECE 667 - Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Introduction to Logic Synthesis Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003

2. ECE 667 - Synthesis & Verification - Lecture 8 2 General Logic Structure Combinational optimization –keep latches/registers at current positions, keep their function –optimize combinational logic in between Sequential optimization –change latch position/function (retiming) Combinational logic (CL) Sequential elements

3. ECE 667 - Synthesis & Verification - Lecture 8 3 Typical Synthesis Scenario - read HDL - control/data flow analysis - basic logic restructuring - crude measures for goals - use logic gates from target cell library - timing optimization - physically driven optimizations RTL to Network Transformation Technology independent Optimizations Technology Mapping Technology Dependent Optimizations Test Preparation - improve testability - test logic insertion

4. ECE 667 - Synthesis & Verification - Lecture 8 4 Local versus Global Transformations Local transformations optimize the function of one node of the network – –smaller area – –better performance – –map to a particular set of cells (library) Global transformations restructure the entire network – –merging nodes – –spitting nodes – –removing/changing connections between nodes Node representation: – –SOP, POS – –BDD – –Factored forms – –keep size bounded to avoid blow-up of local transformations

5. module example(clk, a, b, c, d, f, g, h) input clk, a, b, c, d, e, f; output g, h; reg g, h; always @(posedge clk) begin g = a | b; if (d) begin if (c) h = a&~h; else h = b; if (f) g = c; else a^b; end else if (c) h = 1; else h ^b; end endmodule Specification d a b e f c 0 h g clk Logic Extraction Synthesis Flow a multi-stage process Technology-Independent Optimization f g0 h1 a c e g1 h3 h5 H G b d Technology-Dependent Mapping f d b e a c clk h H G g

7. ECE 667 - Synthesis & Verification - Lecture 8 7 What is Logic Synthesis? D XY Given:Finite-State Machine F(X,Y,Z,, ) where: X: Input alphabet Y: Output alphabet Z: Set of internal states : X x Z Z (next state function, Boolean) : X x Z Y (output function, Boolean) Target:Circuit C(G, W) where: G: set of circuit components  g {Boolean gates, flip-flops, etc} W: set of wires connecting G

8. ECE 667 - Synthesis & Verification - Lecture 8 8 Basic Model of Sequential circuit: FSM X=(x 1,x 2,…,x n ) Y=(y 1,y 2,…,y n )  S=(s 1,s 2,…,s n ) S’=(s’ 1,s’ 2,…,s’ n ) D M(X,Y,S,S 0, , ): X: Inputs Y: Outputs S: Current State S 0 : Initial State(s)  : X  S  S (next state function)  : X  S  Y (output function) Delay elements: Clocked: synchronous single-phase clock, multiple-phase clocks Unclocked: asynchronous Sequential synthesis: find (multi-level) implementation of  (X) and (X) that minimize its cost (area, delay, power)

9. ECE 667 - Synthesis & Verification - Lecture 8 9 Optimization Criteria for Synthesis Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization) Critical path delay of the longest path through the logic Degree of testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g. single or multiple stuck- at faults) Power consumed by the logic gates Noise Immunity Place-ability, Wire-ability The optimization criteria for logic optimization is to minimize some function of: while simultaneously satisfying misc. constraints

10. ECE 667 - Synthesis & Verification - Lecture 8 10 Two-Level (PLA) vs. Multi-Level PLA control logic constrained layout highly automatic technology independent multi-valued logic input, output, state encoding Very predictable Multi-level Logic all logic general (standard cells, macro cells, blocks) automatic partially technology independent part of multi-level logic Very hard to predict E.g. Standard Cell Layout

11. ECE 667 - Synthesis & Verification - Lecture 8 11 Transformation-based Synthesis All modern synthesis systems are build that way – –Series of transformations that change network representation work on uniform network representation – –“script” of “scenario” that can combine those transformations to a overall greedy Transformations differ in: – –their scope local versus global restructuring – –the domain they optimize combinational versus sequential timing versus area technology independent versus technology dependent – – the underlying algorithms they use BDD based, SAT based, structure based, etc.

12. ECE 667 - Synthesis & Verification - Lecture 8 12 Network Representation Boolean network: directed acyclic graph (DAG) node logic function representation f j (x,y) node variable y j : y j = f j (x,y) edge (i,j) if f j depends explicitly on y i Inputs x = (x 1, x 2,…,x n ) Outputs z = (z 1, z 2,…,z p ) External don’t cares: d 1 (x), …, d p (x)

13. ECE 667 - Synthesis & Verification - Lecture 8 13 Sum of Products (SOP) Example: abc’+a’bd+b’d’+b’e’f (sum of cubes) Advantages: easy to manipulate and minimize many algorithms available (e.g. AND, OR, TAUTOLOGY) two-level theory applies Disadvantages: Not representative of logic complexity. For example: f = ad+ae+bd+be+cd+ce f’ = a’b’c’+d’e’ These differ in their implementation by an inverter. Not easy to estimate logic size and performance Difficult to estimate progress during logic manipulation

14. ECE 667 - Synthesis & Verification - Lecture 8 14 Factored Forms Example: (ad+b’c)(c+d’(e+ac’))+(d+e)fg Advantages good representative of logic complexity f=ad+ae+bd+be+cd+ce f’=a’b’c’+d’e’  f=(a+b+c)(d+e) in many designs (e.g. complex gate CMOS) the implementation of a function corresponds directly to its factored form good estimator of logic implementation complexity doesn’t blow up easily Disadvantages not as many algorithms available for manipulation hence often just convert into SOP before manipulation

15. ECE 667 - Synthesis & Verification - Lecture 8 15 Binary Decision Diagrams (BDDs) Like factored form, represents both function and complement Like network of muxes, but restricted since controlled by primary input variables not really a good estimator for implementation complexity Given an ordering, reduced BDD is canonical, hence a good replacement for truth tables For a good ordering, BDDs remain reasonably small for complicated functions (e.g. not multipliers) Manipulations are well defined and efficient True support (dependency) is displayed