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Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.

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Presentation on theme: "Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal."— Presentation transcript:

1 Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram priyas@nvidia.com Vishwani D. Agrawal vagrawal@eng.auburn.edu Hyderabad, India, January 11, 2012

2 Testing of VLSI Circuits and Power High circuit activity during test leads to functional slowdown and high test power dissipation: –Peak power - Large IR drop in power distribution lines Voltage droop and ground bounce (power supply noise) Reduced voltage slows the gates down (delay fault) –Average power - Excessive heating Timing failures Permanent damage to circuit –Good chip may be labeled as bad → yield loss Existing solution: Use worst-case test clock rate to keep average and peak power within specification. –Results in long test time. Jan 11, 2012VLSI Design 20122

3 Problem Statement Reduce test time without exceeding the power specification: Proposed solution: Adaptive test clock Use worst-case clock rate when circuit activity is not known Monitor circuit activity and speed up the clock when activity reduces Jan 11, 2012VLSI Design 20123

4 Previous Publications P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Control in BIST Circuits,” RASDAT, January 2011. P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Control in BIST Circuits,” Proc. 43rd IEEE Southeastern Symposium on System Theory, March 14- 16, 2011, pp. 239-244. P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit,” Proc. 29th IEEE VLSI Test Symposium, May 2-4, 2011, pp. 248-253. P. Shanmugasundaram, Test Time Optimization in Scan Circuits, Master’s Thesis, Department of ECE, Auburn University, Auburn, Alabama, December 2010. Jan 11, 2012VLSI Design 20124

5 Built-In Self-Test (BIST) Jan 11, 2012VLSI Design 2012 5 101010101010 Combinational Logic Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SR: Scan register (flip-flops with dual inputs) SR, RBG and RA have common clock and reset Test multiplexers

6 RBG Generates 010101 Jan 11, 2012VLSI Design 20126 101010101010 Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SR: Scan register (flip-flops with dual inputs) SR, RBG and RA have common clock and reset Test multiplexers

7 RBG Generates 111000 Jan 11, 2012VLSI Design 20127 000111000111 Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SR: Scan register (flip-flops with dual inputs) SR, RBG and RA have common clock and reset Test multiplexers

8 Main Idea Jan 11, 2012VLSI Design 2012 8 Observation: Different sequences of test vector bits consume different amounts of power. Conventional test clock frequency is chosen based on maximum test power consumption. All test vector bits are applied with the same clock frequency. Test vector bit sequences consuming lower power can be applied at higher scan clock frequencies without exceeding power budget of the chip.

9 Scan Clock Frequency Upper bounds: –Maximum shift frequency allowed by shift register structure, F1 –Shift frequency determined by the highest scan activity and peak power budget, F2 –F1 >> F2 Fixed scan clock: use F2 Adaptive clock: monitor activity and vary clock frequency between F1 and F2 Jan 11, 2012VLSI Design 20129

10 Speeding Up Scan Clock Jan 11, 2012VLSI Design 2012 10 Clock periods Cycle power Power budget Clock periods Cycle power Power budget

11 Monitoring Test Activity Jan 11, 2012VLSI Design 201211 101010101010 Combinational Logic Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator Non-transition monitor SR, RBG and RA have common clock and reset Test multiplexers

12 Jan 11, 2012VLSI Design 201212

13 Clock Rate vs. SR Activity Jan 11, 2012VLSI Design 201213 F1 = fmax fmax/2 fmax/3 F2 = fmax/4 0 N/4 2N/4 3N/4 N Number of non-transitions counted Clock rate N N/2 N/4 0 SSR transitions per clock N = number of flip-flops in scan shift register (SR) M = number of adjustable clock rates = 4, in this illustration

14 Jan 11, 2012VLSI Design 201214

15 10/27/201015

16 Externally Tested Circuit Jan 11, 2012VLSI Design 201216

17 Adaptive Clock Testing Jan 11, 2012VLSI Design 201217

18 Test Time Reduction (%) in t512505 Jan 11, 2012VLSI Design 201218 00.10.20.30.40.50.60.65 007.5915.2922.9830.6738.3646.0649.90 0.1007.5915.2922.9830.6738.3642.21 0.20007.5915.2922.9830.6734.52 0.300007.5915.2922.9826.83 0.4000007.5915.2919.13 0.50000007.5911.44 0.600000003.75 0.6500000000

19 Conclusion Dynamic control of scan clock frequency proposed: –Reduces testing time without exceeding power budget. –On-chip activity monitor for self testing circuits keeps track of activity in scan chain and adjusts scan clock rate. –On-chip or off-chip activity monitor can be used for externally tested circuits. –Hand-shake protocol used for communication between ATE and DUT. Vectors with low average scan-in activity and high peak activity achieve large reduction in test time. Method can be implemented in circuits using compression hardware –Activity monitored at every internal scan chain. Up to 50% reduction in test time achieved in circuits when start frequency not pre-determined –Results more significant when start frequency is pre- determined. Jan 11, 2012VLSI Design 201219

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