1. CMOS Transistor and Circuits
Instructed by Shmuel Wimer
Eng. School, Bar-Ilan University
Credits: David Harris
Harvey Mudd College
(Some materials copied/taken/adapted from Harris’ lecture notes)
Jan 2015
CMOS Transistor

2. Outline MOS Capacitor nMOS I-V Characteristics
pMOS I-V Characteristics
DC characteristics and transfer function
Noise margin
Latchup
Pass transistors
Tristate inverter
Jan 2015
CMOS Transistor

3. Introduction So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (DV/Dt) → Dt = (C/I) DV
Capacitance and current determine speed
Also explore what a “degraded level” really means
Jan 2015
CMOS Transistor

4. MOS Capacitor Gate and body form MOS capacitor Operating modes
Accumulation
Depletion
Inversion
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CMOS Transistor

5. Terminal Voltages Mode of operation depends on Vg, Vd, Vs
Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds  0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
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CMOS Transistor

6. nMOS Cutoff
No channel
Ids = 0
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CMOS Transistor

7. nMOS Linear Channel forms Current flows from d to s e- from s to d
Ids increases with Vds
Similar to linear resistor
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CMOS Transistor

8. nMOS Saturation Channel pinches off Ids independent of Vds
We say current saturates
Similar to current source
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CMOS Transistor

9. I-V Characteristics In Linear region, Ids depends on:
How much charge is in the channel
How fast is the charge moving
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CMOS Transistor

10. Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt (Vgc – Vt is the amount of voltage attracting charge to channel beyond the voltage required for inversion)
Jan 2015
CMOS Transistor

11. Carrier velocity Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and drain
v = mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t = L / v
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CMOS Transistor

12. nMOS Linear I-V Now we know How much charge Qchannel is in the channel
How much time t each carrier takes to cross
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CMOS Transistor

13. nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
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CMOS Transistor

14. nMOS I-V Summary Shockley 1st order transistor models Jan 2015
CMOS Transistor

15. Example We will be using a 0.18 mm process for your project tox = 40 Å
m = 180 cm2/V*s
Vt = 0.4 V
Plot Ids vs. Vds
Vgs = 0, 0.3, 0.6, 0.9, 1.2, 1.5 and 1.8V.
Use W/L = 4/2 l
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CMOS Transistor

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CMOS Transistor

17. pMOS I-V All doping and voltages are inverted for pMOS
Mobility mp is determined by holes
Typically 2-3x lower than that of electrons mn
Thus pMOS must be wider to provide same current
In this class, assume mn / mp = 2
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CMOS Transistor

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19. DC Transfer Characteristics
Objective: Find the variation of output voltage Vout for changes in input voltage Vin.
Vtp – Threshold voltage of p-device
Vtn – Threshold voltage of n-device
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CMOS Transistor

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CMOS Transistor

21. Recall CMOS device
CMOS inverter characteristics is derived by solving for Vinn=Vinp and Idsn=-Idsp
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CMOS Transistor

22. CMOS inverter is divided into five regions of operation
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27. I-V Characteristics Make pMOS is wider than nMOS such that bn = bp
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28. Current vs. Vout, Vin
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29. Load Line Analysis For a given Vin: Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in
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30. Load Line Summary
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31. DC Transfer Curve Transcribe points onto Vin vs. Vout plot Jan 2015
CMOS Transistor

32. Operating Regions Revisit transistor operating regions Region nMOS
pMOS A
Cutoff
Linear B
Saturation C D E
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33. Beta Ratio If bp / bn  1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter
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CMOS Transistor

34. DC Transfer function is symmetric for βn=βp
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36. Noise Margin
It determines the allowable noise at the input gate (0/1) so the output (1/0) is not affected
Noise margin is closely related to input-output transfer function
It is derived by driving two inverters connected in series
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CMOS Transistor

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39. Impact of skewing transistor size on noise margin
Increasing (decreasing) P / N ratio increases (decreases) the low noise margin and decreases (increases) the high noise margin
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40. Latchup in CMOS Circuits
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41. Latchup may be induced by power supply glitches or incident radiation
Parasitic bipolar transistors are formed by substrate and source / drain devices
Latchup occurs by establishing a low-resistance paths connecting VDD to VSS
Latchup may be induced by power supply glitches or incident radiation
If sufficiently large substrate current flows, VBE of NPN device increases, and its collector current grows.
This increases the current through RWELL. VBE of PNP device increases, further increasing substrate current.
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CMOS Transistor

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43. If bipolar transistors satisfy βPNP x βNPN > 1, latchup may occur.
Operation voltage of CMOS circuits should be below Vlatchup.
Remedies of latchup problem:
Reduce Rsubstrate by increasing P doping of substrate by process control.
Reducing RWELL and resistance of WELL contacts by process control.
Layout techniques: separation of P and N devices, guard rings, many WELL contacts (at design).
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CMOS Transistor

44. Pass Transistors We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing VDD
Vg = VDD
If Vs > VDD-Vt => Vgs < Vt
Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded “1”
Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
Jan 2015
CMOS Transistor

45. Pass Transistor CKTs
As the source can rise to within a threshold voltage of the gate, the
output of several transistors in series is no more degraded than that
of a single transistor.
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CMOS Transistor

46. Transmission Gates Single pass transistors produce degraded outputs
Complementary Transmission gates pass both 0 and 1 well
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47. Transmission gate ON resistance as input voltage sweeps from 0 to 1(VSS to VDD), assuming that output follows closely.
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48. Tristates Tristate buffer produces Z when not enabled EN A Y Z 1Z 1
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49. Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
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50. Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
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CMOS Transistor

51. Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1X 1
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CMOS Transistor

52. Gate-Level Mux Design How many transistors are needed? 20 Jan 2015
CMOS Transistor

53. Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors
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54. Inverting Mux Inverting multiplexer Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
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CMOS Transistor

55. 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
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56. Sizing for Performance
NMOS and PMOS diffusion + diffusion-gate overlap.
Fan-out (input gates) + interconnects.
Equivalent gate resistance.
Capacitive load of an inverter.
S sizing factor.
Propagation delay:
Inverter delay loaded only by intrinsic.
Jan 2015
CMOS Transistor

57. Intrinsic cap to gate cap ratio ≈1.
Effective fan-out.
The delay of an inverter is only a function of the ratio between its external load cap to its input cap 1 2 N In
Out
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CMOS Transistor

58. It implies that same sizing factor f is used for all stages.
imply
It implies that same sizing factor f is used for all stages.
The optimal size of an inverter is the geometric mean of its neighbor drives
Given and , and the optimal sizing factor is
The minimum delay through the chain is
Jan 2015
CMOS Transistor

59. What should be the optimal N ?
The derivative by N of yields
or equivalently
having a closed form solution
only for γ=0, a case where the intrinsic self load is ignored and only the fan-out is considered.
Jan 2015
CMOS Transistor