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Tutorial #10 MIPS commands 234262 – © Yohai Devir 2007 Technion - IIT
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MIPS is a simple processor: All arithmetic operations are done with registers only. Memory access is done with only two instructions – LW\ SW. The MIPS is a 32 -bit machine. The instructions are 32 -bits long. Register file (RF), with 32 registers of 32 bits each (5 bit for the number) Memory address size – 32 bits. We’ll work in resolution of words – 32 bit each. 234262 – © Yohai Devir 2007 Technion - IIT
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There are registers which are denoted by R0, R1,…R31. Register 0 is read-only and its value is 0 ( R0 ≡ 0 ). The PC (Program Counter) is a special register. The PC points to the next instruction to be executed. In some places register K is marked as $K (i.e. R8 ≡ $8) 234262 – © Yohai Devir 2007 Technion - IIT
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(maximal) size 2 30 words of 32 bits each. Each word has a 32 -bit address, the two LSB bits of the address are ’ 00 ’. Memory can be accessed by LW or SW commands only. 234262 – © Yohai Devir 2007 Technion - IIT
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3 types of instructions, each kind with a fixed structure: Type R (Register) Type I (Immediate) Type J (Jump) 234262 – © Yohai Devir 2007 Technion - IIT
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Tutorial #11 Multicycle MIPS 234262 – © Yohai Devir 2007 Technion - IIT
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234262 – © Yohai Devir 2007 Technion - IIT
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234262 – © Yohai Devir 2007 Technion - IIT ALUALU M6 M6 M5 M5 REG FILE M4 M4 M3 M3 IRIR M2 M2 M1 M1 PCPC MEM BPCBPC 12 IR[OP+FUN] ZERO C1 C3 WRITEWRITE 6 IR[OP] ZERO C2 WRITEWRITE READREAD
![– © Yohai Devir 2007 Technion - IIT ALUALU M6 M6 M5 M5 REG FILE M4 M4 M3 M3 IRIR M2 M2 M1 M1 PCPC MEM BPCBPC 12 IR[OP+FUN] ZERO C1 C3 WRITEWRITE 6 IR[OP] ZERO C2 WRITEWRITE READREAD](http://images.slideplayer.com/15/4844780/slides/slide_8.jpg "– © Yohai Devir 2007 Technion - IIT ALUALU M6 M6 M5 M5 REG FILE M4 M4 M3 M3 IRIR M2 M2 M1 M1 PCPC MEM BPCBPC 12 IR[OP+FUN] ZERO C1 C3 WRITEWRITE 6 IR[OP] ZERO C2 WRITEWRITE READREAD")
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234262 – © Yohai Devir 2007 Technion - IIT ALUALU ZERO C3 ALUout
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234262 – © Yohai Devir 2007 Technion - IIT WRITEWRITE READREAD ADDR MEMout MEM WDATA
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234262 – © Yohai Devir 2007 Technion - IIT N REG1 W DATA R s R t N REG2 WN REG REG FILE WRITEWRITE W DATA WN REG N REG1 N REG2 R s R t 31*32 WRITE
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Rs R31R1 Nreg1 נתב כתיבה נתב קריאה #1 נתב קריאה #2 Nreg2 WNreg WData WRITE Rt 234262 – © Dima Elenbogen 2010 Technion - IIT הערה : הנתבים צירופיים !
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IRIR M5 M5 M6 M6 ALUALU 4 ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA IR ← Mem[PC] PC ← PC + 4 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT
![IRIR M5 M5 M6 M6 ALUALU 4 ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA IR ← Mem[PC] PC ← PC – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT](http://images.slideplayer.com/15/4844780/slides/slide_13.jpg "IRIR M5 M5 M6 M6 ALUALU 4 ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA IR ← Mem[PC] PC ← PC – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT")
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OPeration Source \ Target Registers IMmediate 234262 – © Yohai Devir 2007 Technion - IIT OPRsRtIM 6 bit5 bit 16 bit
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Branch on Not Equal Semantic: if R 31 ≠R8, the next instruction to be executed is the on which is stored in the memory at label ‘loop1’ BEQ branches if EQual OPRsRtIM 4318? 6 bit5 bit 16 bit 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT
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We want to branch to address 00…001000. However, this a 32bit address while having only 16bit of IM. Most branches are to “nearby” addresses. We can put address relative to the PC. 2 LSB bits are ’00 (Why?) No need to specify the 2 LSBs. We’ll see this later: After bringing the intruction (before really reading it) the PC is incremented in 4 bytes. 234262 – © Yohai Devir 2007 Technion - IIT (BNE addr )PC new (BNE addr +4)+IM x 4
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 RsRs RtRt M5 M5 M6 M6 ALUALU N REG2 REG FILE 16 IR[IM] 44 SIGN EXT C1 6 IR[OP] ALUout BPCBPC PCPC C1 is decoding IR[OP] Rs is being read Rt is being read BPC ← PC + SX(Imm)*4
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 RsRs RtRt M5 M5 M6 M6 ALUALU N REG2 REG FILE 16 IR[IM] 44 SIGN EXT C1 6 IR[OP] ALUout BPCBPC PCPC C1 is decoding IR[OP] Rs is being read Rt is being read BPC ← PC + SX(Imm)*4](http://images.slideplayer.com/15/4844780/slides/slide_17.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 RsRs RtRt M5 M5 M6 M6 ALUALU N REG2 REG FILE 16 IR[IM] 44 SIGN EXT C1 6 IR[OP] ALUout BPCBPC PCPC C1 is decoding IR[OP] Rs is being read Rt is being read BPC ← PC + SX(Imm)*4")
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OPeration Source \ Target \ Destination Register SHift AMounT FUNCtion 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT OPRsRtRdshamtfunc 6 bit5 bit 6 bit Rs מיועד לקריאה בלבד Rt מיועד לקריאה ולכתיבה ( לכתיבה בחלק של פקודות מסוג I) Rd מיועד לכתיבה בלבד ומופיע בפקודות מסוג R בלבד
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Semantic: R11 R22 + R31 234262 – © Yohai Devir 2007 Technion - IIT OPRsRtRdshamtfunc 0223111032 6 bit5 bit 6 bit OPRsRtRdshamtfunc 00000010110111110101100000100000 6 bit5 bit 6 bit OPRsRtRdshamtfunc 6 bit5 bit 6 bit
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234262 – © Yohai Devir 2007 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2
![– © Yohai Devir 2007 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2](http://images.slideplayer.com/15/4844780/slides/slide_20.jpg "– © Yohai Devir 2007 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 1)Fetch 2)Decode 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 1)Fetch 2)Decode 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout](http://images.slideplayer.com/15/4844780/slides/slide_21.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 1)Fetch 2)Decode 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout")
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234262 – © Yohai Devir 2007 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU OPRsRtIM 82211-12 6 bit5 bit 16 bit
![– © Yohai Devir 2007 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU OPRsRtIM bit5 bit 16 bit](http://images.slideplayer.com/15/4844780/slides/slide_22.jpg "– © Yohai Devir 2007 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU OPRsRtIM bit5 bit 16 bit")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-WB)Rt ← ALUout
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-WB)Rt ← ALUout](http://images.slideplayer.com/15/4844780/slides/slide_23.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-WB)Rt ← ALUout")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 M5 M5 R s R t M6 M6 N REG2 16 IR[IM] ZERO REG FILE 4 44 SIGN EXT ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO C2 ALUout ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) if (zero) PC ← BPC
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 M5 M5 R s R t M6 M6 N REG2 16 IR[IM] ZERO REG FILE 4 44 SIGN EXT ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO C2 ALUout ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) if (zero) PC ← BPC](http://images.slideplayer.com/15/4844780/slides/slide_24.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 M5 M5 R s R t M6 M6 N REG2 16 IR[IM] ZERO REG FILE 4 44 SIGN EXT ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO C2 ALUout ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) if (zero) PC ← BPC")
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234262 – © Yohai Devir 2007 Technion - IIT ALUALU M6 M6 M5 M5 REG FILE M4 M4 M3 M3 IRIR M2 M2 M1 M1 PCPC MEM BPCBPC 12 IR[OP+FUN] ZERO C1 C3 WRITEWRITE 6 IR[OP] ZERO C2 WRITEWRITE READREAD
![– © Yohai Devir 2007 Technion - IIT ALUALU M6 M6 M5 M5 REG FILE M4 M4 M3 M3 IRIR M2 M2 M1 M1 PCPC MEM BPCBPC 12 IR[OP+FUN] ZERO C1 C3 WRITEWRITE 6 IR[OP] ZERO C2 WRITEWRITE READREAD](http://images.slideplayer.com/15/4844780/slides/slide_25.jpg "– © Yohai Devir 2007 Technion - IIT ALUALU M6 M6 M5 M5 REG FILE M4 M4 M3 M3 IRIR M2 M2 M1 M1 PCPC MEM BPCBPC 12 IR[OP+FUN] ZERO C1 C3 WRITEWRITE 6 IR[OP] ZERO C2 WRITEWRITE READREAD")
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Load Word Semantic: Read the word located in the memory address of [R3] + 300 (not 303 !!!) and write it to R23 NOTE: Rs is the Base register Rt is the register to write to. 234262 – © Yohai Devir 2007 Technion - IIT OPRsRtIM 35323300 6 bit5 bit 16 bit
![Load Word Semantic: Read the word located in the memory address of [R3] (not 303 !!!) and write it to R23 NOTE: Rs is the Base register Rt is the register to write to.](http://images.slideplayer.com/15/4844780/slides/slide_26.jpg "– © Yohai Devir 2007 Technion - IIT OPRsRtIM bit5 bit 16 bit.")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-MEM)MEMout <= Mem[ALUout] 5-WB)Rt ← MEMout
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-MEM)MEMout <= Mem[ALUout] 5-WB)Rt ← MEMout](http://images.slideplayer.com/15/4844780/slides/slide_27.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 16 IR[IM] WN REG REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-MEM)MEMout <= Mem[ALUout] 5-WB)Rt ← MEMout")
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Load Word Semantic: Writes the word located in R7 to the memory address of [R6] + 200 (not 206!!!) NOTE: Rs is the Base register Rt is the read from. 234262 – © Yohai Devir 2007 Technion - IIT OPRsRtIM 4367200 6 bit5 bit 16 bit
![Load Word Semantic: Writes the word located in R7 to the memory address of [R6] (not 206!!!) NOTE: Rs is the Base register Rt is the read from.](http://images.slideplayer.com/15/4844780/slides/slide_28.jpg "– © Yohai Devir 2007 Technion - IIT OPRsRtIM bit5 bit 16 bit.")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 M5 M5 R s R t M6 M6 16 IR[IM] REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 N REG2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-MEM)Mem[ALUout] ← Rt
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 M5 M5 R s R t M6 M6 16 IR[IM] REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 N REG2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-MEM)Mem[ALUout] ← Rt](http://images.slideplayer.com/15/4844780/slides/slide_29.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 M5 M5 R s R t M6 M6 16 IR[IM] REG FILE 4 SIGN EXT ALUout PCPC M1 M1 M2 M2 N REG2 ADDR MEMout MEM WDATA ALUALU 1)Fetch 2)Decode 3- EX) ALUout <= Rs + SX(Imm) 4-MEM)Mem[ALUout] ← Rt")
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OPeration eXtended Immediate Unconditional jumps 2 LSBs are ’00’. No need to specify them. 4 MSBs are taken from PC 234262 – © Yohai Devir 2007 Technion - IIT OPXI 6 bit26 bits
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Assume that there is a J instruction in the following address : 0xCE125678:J 0xCF444444 It jumps to a specific address. Semantic: PC new PC [upper 4 MSBs] || XI || 00 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT OPXI 2 0x03D1 1111 6 bit26 bits
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR PCPC M1 M1 M2 M2 IR[XI] 26 PC[31:28] 4 C1 6 IR[OP] 2 0 ADDR MEMout MEM WDATA 1)Fetch 2)Decode 3- EX) PC ← PC[31:28] || XI*4 ב -EX ה -ALU לא בשימוש, אך עדיין עליו לבצע איזשהו חישוב סרק על מנת למנוע אות סטטוס zero מזוהם. למשל, ALUout <= PC + 4
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR PCPC M1 M1 M2 M2 IR[XI] 26 PC[31:28] 4 C1 6 IR[OP] 2 0 ADDR MEMout MEM WDATA 1)Fetch 2)Decode 3- EX) PC ← PC[31:28] || XI*4 ב -EX ה -ALU לא בשימוש, אך עדיין עליו לבצע איזשהו חישוב סרק על מנת למנוע אות סטטוס zero מזוהם.](http://images.slideplayer.com/15/4844780/slides/slide_32.jpg "למשל, ALUout <= PC + 4.")
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234262 – © Yohai Devir 2007 Technion - IIT IR (PC)MEM PC PC+4 REG2 Rt ;REG1 Rs BPC PC + 4 SX(IM ) FETCH PC[27:0] 4 XI FETCH OP= ’J’ ALUout Rs Rt IF(Rs=Rt) PC BPC FETCH OP= ’BEQ’ DECODE ALUout f (Rs, Rt) f מצוין ב - IR[FUN] FETCH ALUout Rs + SX(IM) OP = ’LW’ or ‘SW’ ALUout f (Rs, SX(IM)) f מצוין ב - IR[OP] I מסוג OP ( קריאה ) MEMout MEM(ALUout) (כתיבה בזיכרון) MEM(ALUout) Rt Rt MEMout FETCH Rt ALUout FETCH OP= ’SW’ OP= ‘LW’ Rd ALUout R מסוג OP
![– © Yohai Devir 2007 Technion - IIT IR (PC)MEM PC PC+4 REG2 Rt ;REG1 Rs BPC PC + 4 SX(IM ) FETCH PC[27:0] 4 XI FETCH OP= ’J’ ALUout Rs Rt IF(Rs=Rt) PC BPC FETCH OP= ’BEQ’ DECODE ALUout f (Rs, Rt) f מצוין ב - IR[FUN] FETCH ALUout Rs + SX(IM) OP = ’LW’ or ‘SW’ ALUout f (Rs, SX(IM)) f מצוין ב - IR[OP] I מסוג OP ( קריאה ) MEMout MEM(ALUout) (כתיבה בזיכרון) MEM(ALUout) Rt Rt MEMout FETCH Rt ALUout FETCH OP= ’SW’ OP= ‘LW’ Rd ALUout R מסוג OP](http://images.slideplayer.com/15/4844780/slides/slide_33.jpg "– © Yohai Devir 2007 Technion - IIT IR (PC)MEM PC PC+4 REG2 Rt ;REG1 Rs BPC PC + 4 SX(IM ) FETCH PC[27:0] 4 XI FETCH OP= ’J’ ALUout Rs Rt IF(Rs=Rt) PC BPC FETCH OP= ’BEQ’ DECODE ALUout f (Rs, Rt) f מצוין ב - IR[FUN] FETCH ALUout Rs + SX(IM) OP = ’LW’ or ‘SW’ ALUout f (Rs, SX(IM)) f מצוין ב - IR[OP] I מסוג OP ( קריאה ) MEMout MEM(ALUout) (כתיבה בזיכרון) MEM(ALUout) Rt Rt MEMout FETCH Rt ALUout FETCH OP= ’SW’ OP= ‘LW’ Rd ALUout R מסוג OP")
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234262 – © Yohai Devir 2007 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU
![– © Yohai Devir 2007 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU](http://images.slideplayer.com/15/4844780/slides/slide_34.jpg "– © Yohai Devir 2007 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT M3 M3 M4 M4 M5 M5 M6 M6 M1 M1 M2 M2 בפועל כל ה -MUX- ים במעבד הם אדישים. אבל לא כולם מוכרחים להיות כאלה : אדום – חייב להיות אדיש סגול – תלוי במימוש של הזיכרון ( האם הפלט לוגי כשלא קוראים ולא כותבים ) ירוק – רשאי להיות לא אדיש אותות בקרה לבוררים האדומים חייבים להגיע ישירות מתוך FF- ים חסרי ספחות סטטיות של הבקר !
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IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT אותות בקרה לבוררים האדומים חייבים להגיע ישירות מתוך FF- ים חסרי ספחות סטטיות של הבקר !
![IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT אותות בקרה לבוררים האדומים חייבים להגיע ישירות מתוך FF- ים חסרי ספחות סטטיות של הבקר !](http://images.slideplayer.com/15/4844780/slides/slide_36.jpg "IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT אותות בקרה לבוררים האדומים חייבים להגיע ישירות מתוך FF- ים חסרי ספחות סטטיות של הבקר !")
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Jump And Link Assume that there is a JAL instruction in the following address : 0xEE125678:JAL 0xEF444444 Stores PC in Register 31 and then jumps to given address. Semantic: R 31 PC PC PC [upper 4 MSBs] || XI || 00 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT OPXI 3 0x03D1 1111 6 bit26 bits
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU 5 31 32
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU](http://images.slideplayer.com/15/4844780/slides/slide_38.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT 1)Fetch 2)Decode 3- EX) R31 ← PC PC ← PC[31:28] || XI*4
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT 1)Fetch 2)Decode 3- EX) R31 ← PC PC ← PC[31:28] || XI*4](http://images.slideplayer.com/15/4844780/slides/slide_39.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT 1)Fetch 2)Decode 3- EX) R31 ← PC PC ← PC[31:28] || XI*4")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT הרעיון : ננצל מסלול צירופי מ -PC ל -M4 העובר דרך ALU. כלומר, נבצע : R 31 ← PC + 0 בעיה: ערך 0 היינו יכולים לקרוא מ-R0 אבל אין בקידוד הפקודה קבוע 0 ולכן לא נוכל לקרוא את R0 (אלא אם נוסיף MUX לפני Nreg1). PC + 0 ≡ PC + 4 – 4 פיתרון: נשתמש בזהות: PC + 0 ≡ PC + 4 – 4
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT 1)Fetch// PC ← α + 4, 2)Decode 3- EX1) PC ← PC + 4 // PC ← α + 8 4- EX2)ALUout <= PC – 4 // ALUout <= α + 4 5- WB)R31 ← ALUout // R31 ← α + 4 PC ← PC[31:28] || XI*4 // J כמו // α is the address of the current (JAL) command
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT 1)Fetch// PC ← α + 4, 2)Decode 3- EX1) PC ← PC + 4 // PC ← α EX2)ALUout <= PC – 4 // ALUout <= α WB)R31 ← ALUout // R31 ← α + 4 PC ← PC[31:28] || XI*4 // J כמו // α is the address of the current (JAL) command](http://images.slideplayer.com/15/4844780/slides/slide_41.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT 1)Fetch// PC ← α + 4, 2)Decode 3- EX1) PC ← PC + 4 // PC ← α EX2)ALUout <= PC – 4 // ALUout <= α WB)R31 ← ALUout // R31 ← α + 4 PC ← PC[31:28] || XI*4 // J כמו // α is the address of the current (JAL) command")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU](http://images.slideplayer.com/15/4844780/slides/slide_42.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU")
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IRIR M5 M5 M6 M6 ALUALU 4 ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IR ← Mem[PC] PC ← PC + 4
![IRIR M5 M5 M6 M6 ALUALU 4 ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IR ← Mem[PC] PC ← PC + 4](http://images.slideplayer.com/15/4844780/slides/slide_43.jpg "IRIR M5 M5 M6 M6 ALUALU 4 ALUout PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IR ← Mem[PC] PC ← PC + 4")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE ALUout 12 IR[OP+FUN] C3 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE ALUout 12 IR[OP+FUN] C3 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout](http://images.slideplayer.com/15/4844780/slides/slide_44.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE ALUout 12 IR[OP+FUN] C3 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout IR ← Mem[PC] PC ← PC + 4 כנגד
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout IR ← Mem[PC] PC ← PC + 4 כנגד](http://images.slideplayer.com/15/4844780/slides/slide_45.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 3- EX) ALUout <= Rs + Rt 4-WB)Rd ← ALUout IR ← Mem[PC] PC ← PC + 4 כנגד")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 3- EX) RWD ←Rs + Rt 4-WB)Rd ← RWD IR ← Mem[PC] PC ← PC + 4 W DATA RWDRWD add pre-fetch
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 3- EX) RWD ←Rs + Rt 4-WB)Rd ← RWD IR ← Mem[PC] PC ← PC + 4 W DATA RWDRWD add pre-fetch](http://images.slideplayer.com/15/4844780/slides/slide_46.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT ADDR MEMout MEM WDATA IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 M5 M5 R s R t M6 M6 ALUALU N REG2 WN REG REG FILE 4 ALUout PCPC M1 M1 M2 M2 12 IR[OP+FUN] C3 3- EX) RWD ←Rs + Rt 4-WB)Rd ← RWD IR ← Mem[PC] PC ← PC + 4 W DATA RWDRWD add pre-fetch")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU שימו לב כי pre-fetching לא מתרחש תוך כדי ביצוע פקודות : קפיצה והסתעפות SW RWDRWD
![– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU שימו לב כי pre-fetching לא מתרחש תוך כדי ביצוע פקודות : קפיצה והסתעפות SW RWDRWD](http://images.slideplayer.com/15/4844780/slides/slide_47.jpg "– © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU שימו לב כי pre-fetching לא מתרחש תוך כדי ביצוע פקודות : קפיצה והסתעפות SW RWDRWD")
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OP= ’BEQ’ OP = ’LW’ or ‘SW’ I מסוג OP R מסוג OP IR (PC)MEM PC PC+4 REG2 Rt ;REG1 Rs BPC PC + 4 SX(IM ) FETCH PC[27:0] 4 XI FETCH OP= ’J’ ALUout Rs Rt IF(Rs=Rt) PC BPC FETCH DECODE RWD ← f (Rs, Rt) f מצוין ב - IR[FUN] DECODE ALUout Rs + SX(IM) RWD ← f (Rs, SX(IM)) f מצוין ב - IR[OP] ( קריאה ) RWD ← MEM(ALUout) (כתיבה בזיכרון) MEM(ALUout) Rt FETCH Rt RWD IR ← MEM(PC) PC ← PC + 4 DECODE OP= ’SW’ OP= ‘LW’ Rd RWD IR ← MEM(PC) PC ← PC + 4 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT שימו לב כי pre-fetching לא מתרחש תוך כדי ביצוע פקודות : קפיצה והסתעפות SW
![OP= ’BEQ’ OP = ’LW’ or ‘SW’ I מסוג OP R מסוג OP IR (PC)MEM PC PC+4 REG2 Rt ;REG1 Rs BPC PC + 4 SX(IM ) FETCH PC[27:0] 4 XI FETCH OP= ’J’ ALUout Rs Rt IF(Rs=Rt) PC BPC FETCH DECODE RWD ← f (Rs, Rt) f מצוין ב - IR[FUN] DECODE ALUout Rs + SX(IM) RWD ← f (Rs, SX(IM)) f מצוין ב - IR[OP] ( קריאה ) RWD ← MEM(ALUout) (כתיבה בזיכרון) MEM(ALUout) Rt FETCH Rt RWD IR ← MEM(PC) PC ← PC + 4 DECODE OP= ’SW’ OP= ‘LW’ Rd RWD IR ← MEM(PC) PC ← PC – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT שימו לב כי pre-fetching לא מתרחש תוך כדי ביצוע פקודות : קפיצה והסתעפות SW](http://images.slideplayer.com/15/4844780/slides/slide_48.jpg "OP= ’BEQ’ OP = ’LW’ or ‘SW’ I מסוג OP R מסוג OP IR (PC)MEM PC PC+4 REG2 Rt ;REG1 Rs BPC PC + 4 SX(IM ) FETCH PC[27:0] 4 XI FETCH OP= ’J’ ALUout Rs Rt IF(Rs=Rt) PC BPC FETCH DECODE RWD ← f (Rs, Rt) f מצוין ב - IR[FUN] DECODE ALUout Rs + SX(IM) RWD ← f (Rs, SX(IM)) f מצוין ב - IR[OP] ( קריאה ) RWD ← MEM(ALUout) (כתיבה בזיכרון) MEM(ALUout) Rt FETCH Rt RWD IR ← MEM(PC) PC ← PC + 4 DECODE OP= ’SW’ OP= ‘LW’ Rd RWD IR ← MEM(PC) PC ← PC – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT שימו לב כי pre-fetching לא מתרחש תוך כדי ביצוע פקודות : קפיצה והסתעפות SW")
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234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT מה היה קורה אילו היינו שמים את הרגיסטר RWD ביציאה של ה -ALU?
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IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU RWDRWD 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT אחרי שינוי קל שלא עולה כלום מקבלים פיתרון סביר אם כי חלש יותר. הפיתרון הראשון איפשר prefetching גם בסוף ביצוע LW.
![IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU RWDRWD – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT אחרי שינוי קל שלא עולה כלום מקבלים פיתרון סביר אם כי חלש יותר.](http://images.slideplayer.com/15/4844780/slides/slide_50.jpg "הפיתרון הראשון איפשר prefetching גם בסוף ביצוע LW..")
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IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M7 M7 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU החל במחזור 3 הבקר יודע האם ניתן לשכוח את הכתובת השמורה ב-BPC. ניתן לוותר בכלל על בורר M4 מכיוון ש-Wdata מקבל את כל ערכיו מ-BPC. עלות השינויים: 0! הסבנו את BPC כך שימלא גם את תפקידו של RWD. 234262 – © Yohai Devir 2007 Dima Elenbogen 2011 Technion - IIT
![IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M7 M7 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU החל במחזור 3 הבקר יודע האם ניתן לשכוח את הכתובת השמורה ב-BPC.](http://images.slideplayer.com/15/4844780/slides/slide_51.jpg "ניתן לוותר בכלל על בורר M4 מכיוון ש-Wdata מקבל את כל ערכיו מ-BPC. עלות השינויים: 0. הסבנו את BPC כך שימלא גם את תפקידו של RWD – © Yohai Devir 2007 Dima Elenbogen 2011 Technion - IIT.")
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