1. Project Status Risks BOM Analysis Feasibility Designs Test Plans

2. Electronic System

3. FPGA Board Diagram

4. FPGA Board to Scale

5. Electronic System

6. OEM Board

7. 1.Integrate supplied components A.10MP Visual Band Camera B.1.3MP IR Camera C.Spatial Sensors i.NovAtel OEM Board OEMV3 ii.NovAtel OEM Board OEMV2 D.Camera Processing Board 2.Capture data from two cameras 3.Capture 10MP @ 1fps 4.Capture 1.3MP @ 30fps 5.Capture INS data @ 30/sec (simultaneously) Processing elements Customer Needs Met 6.External INS units 7.Data processing (overlay) 8.Real time viewing 9.Store full-res. Data during flight 10. Support NovAtel GNSS board

8. 1.Integrate supplied components A.10MP Visual Band Camera B.1.3MP IR Camera C.Spatial Sensors i.NovAtel OEM Board OEMV3 ii.NovAtel OEM Board OEMV2 D.Camera Processing Board 2.Capture data from two cameras 3.Capture 10MP @ 1fps 4.Capture 1.3MP @ 30fps 5.Capture INS data @ 30/sec (simultaneously) Processing elements Customer Needs Met 6.External INS units 7.Data processing (overlay) 8.Real time viewing 9.Store full-res. Data during flight 10. Support NovAtel GNSS board

9. 1.Integrate supplied components A.10MP Visual Band Camera B.1.3MP IR Camera C.Spatial Sensors i.NovAtel OEM Board OEMV3 ii.NovAtel OEM Board OEMV2 D.Camera Processing Board 2.Capture data from two cameras 3.Capture 10MP @ 1fps 4.Capture 1.3MP @ 30fps 5.Capture INS data @ 30/sec (simultaneously) Processing elements Customer Needs Met 6.External INS units 7.Data processing (overlay) 8.Real time viewing 9.Store full-res. Data during flight 10. Support NovAtel GNSS board

10. 1.Integrate supplied components A.10MP Visual Band Camera B.1.3MP IR Camera C.Spatial Sensors D.Camera Processing Board 2.Capture data from two cameras 3.Capture 10MP @ 1fps 4.Capture 1.3MP @ 30fps 5.Capture INS data @ 30/sec (simultaneously) Processing elements Customer Needs Met 6.External INS units 7.Data processing (overlay) 8.Real time viewing 9.Store full-res. Data during flight 10. Support NovAtel GNSS board

11. FPGA Inputs/Outputs Flexible Architecture Faster Speed Parallel Processing DSP Energy Efficient Single Pipeline Easy Implementation Math based ISA Processing Elements

12. DSP Customer programmable – Encoding/Decoding media – Peripherals Role in this design – Image compression – Real time streaming of data – INS interface Required skills – Implementable Knowledge of C – DSP/BIOS

13. FPGA FPGA Selection – Quicker time to fabrication – Supreme configurability/Field reprogrammable – Has the I/O needed – Parallel processing

14. FPGA Xilinx Selection – Resources available to the team – Larger range of choices than other companies – Customer preference Model XC6SLX75T Selection – Package size (23mm x 23mm) – High speed transceiver count – I/O pin count – Cost effectiveness

15. Data Flow – Initial Design Pictures Camera  FPGA  OEM INS Data INS  OEM

16. Data Flow – Final Design Pictures Camera  FPGA  OEM Camera  FPGA  HD INS Data INS  OEM  FPGA  HD

17. Data Speeds **Note: baud = bits per second (RS-232) Image – IR: 30 images / second VGA=640x480 9.2 MHz – Visible :1 image / second 10.7MP=3664x2748 10.07 MHz INS – 30 captures / second 1kB=8kb 8000 baud

18. FPGA Pin Speeds Minimum values – 13ns -> 76 MHz – 5ns -> 200 MHz

19. System Software Design

20. FPGA Image Controller

21. System Software Design

22. FPGA Central Dispatch

23. FPGA Process Flowchart Backup

24. FPGA Configurability Basis of configurability – Nature of transistor based FPGA Physical limitations – Through header on PCB using Xilinx provided development tools Backup

25. FPGA Configurability Customer configurable – Configuration languages Knowledge of VHDL/Verilog – Development packages Xilinx provided development tools – Physical configuration requirements Connect programmer and download data file, restart board Backup

26. Processing Elements DSP CPU based C Language FPGA Transistor based VHDL/Verilog Backup