1. A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research Cindy Mark Prof. Steve Wilton University of British Columbia Supported by Altera and NSERC

2. Introduction: Overview FPGA architecture studies require benchmark circuits  Realistic, big, and varied Current circuits are small  MCNC: 24 LE to 7694 LE  Stratix III: 19,000 LE to 135,200 LE  Alternatives ASIC: requires conversion Synthetic: designed for sizes similar to MCNC circuits Contribution: SOC synthetic circuit generator  Glues modules into realistic, big netlists  Allows customization of the circuit content

3. Research Approach Survey of Circuit Designs Generator Development

4. Circuit Characterization: Survey 66 Block Diagrams  24 industrial  42 academic Applications:  Communication  Multimedia  Processor

5. Circuit Model Leaf Modules  Processor  Interface  Controller  Cores Networks  Bus  Dataflow  Star Leaf modules connected by networks Networks are hierarchical, and arranged in a tree

6. Circuit Model: Example

7. Circuit Characterization: Trends Hierarchy Depth Distribution 1 2 3 4

8. Circuit Characterization: Trends Max Hier. Depth Average # Networks 11 21.81 31.75 42.16 Network # Distribution on Level 2

9. Circuit Characterization: Trends Number of Modules per Bus Number of Modules per Dataflow Number of Modules per Star

10. Generation

11. Circuit Generator: Overview Constraints file:  # hierarchy levels, # blocks, # networks, bus width  Can specify any combination One BLIF library directory per module type

12. Circuit Generation: Example 1 2 3 4

13. Circuit Generator: Implementation Modules  MCNC  OpenCores  Synthetic Networks  Bus: AMBA single master  Dataflow: with feedback  Star: no feedback

14. Circuit Generator: Implementation Reset Interrupt Where are the fine grained connections? Some generated through the network process

15. Comparison: Overview Evaluation of SOC circuits as they scale Comparison to other synthetic generators  GEN: purely combinational  GNL: FFs and IOs Characteristics  Post-Routing: channel width, wirelength, crit. path

16. Results: Locality GNL New

17. Results: Average Wirelength

18. Results: Channel Width

19. Results: Critical Path Delay

20. Conclusion: Limitations High number of IO pins  Caused by star networks  Mismatch between bus width and module IO pins  Head and tail of dataflow networks

21. Conclusion: Ongoing work Add different block types (memory) Add different network types Improve the modeling of reset, interrupt Improve the modeling of blocks

22. Conclusion: Status Can generate circuits 150k LE and up Works on Linux / Windows  Works better on Linux Manual Available for download:  www.ece.ubc.ca/~cindym/

23. Conclusion: Summary We have developed a synthetic SOC circuit generator suitable for architectural research  Based on an analysis of published block diagrams  Assumes a tree-like network hierarchy that connects existing BLIF blocks  Resulting circuits, in general, display slower growth in complexity and post-routing characteristics relative to GEN and GNL.

24. Thank You!

25. Results: Rent Parameter

26. Results: Nets (post-clustering)

27. Introduction: Outline Characterization of Current SOC Circuits Circuit Model Generation Comparison against GEN, and GNL Conclusion