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Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 221 Lecture 22 Delta I DDQ Testing and Built-In Current Testing n Current limit setting n Testing.

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Presentation on theme: "Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 221 Lecture 22 Delta I DDQ Testing and Built-In Current Testing n Current limit setting n Testing."— Presentation transcript:

1 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 221 Lecture 22 Delta I DDQ Testing and Built-In Current Testing n Current limit setting n Testing time issues Delta I DDQ testing (  I DDQ ) n Built-in current testing sensors n Summary

2 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 222 Current Limit Setting Should try to get it < 1  A n Histogram for 32 bit microprocessor

3 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 223 Hewlett-Packard / Sandia Laboratories Results n HP – static CMOS standard cell, 8577 gates, 436 FF n Sandia Laboratories – 5000 static RAM tests n Reject rate for various tests: Com- pany HP San- dia Reject Rates (%) Without I DDQ With I DDQ Without I DDQ With I DDQ Neither 16.46 0.80 No Scan/ Funct. 6.36 0.09 Scan/ No Funct. 6.04 0.11 Both 5.80 0.00 Functional Tests 5.562 0 Scan and Functional Tests

4 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 224 Failure Distribution in Hewlett-Packard Chip

5 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 225 % Functional Failures After 100 Hours Life Test Work of McEuen at Ford Microelectronics

6 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 226 Lower / Upper I DDQ Test Time Limits – McEuen (Ford)

7 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 227 Delta I DDQ Testing -- Thibeault n Use derivative of I DDQ at test vector as current signature  I DDQ (i) = I DDQ (i) – I DDQ (i – 1) n Leads to a narrower histogram n Eliminates variation between chips and between wafers n P – probability of false test decisions

8 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 228 I DDQ Versus  I DDQ

9 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 229 Difference in Histograms n A – test escapes, B – yield loss

10 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2210 Parameters for Estimating P  def -- minimum |  I DDQ | peak from active defect,  g = good mean,  b = bad mean Symbol P iddq  gi  def  gi +  def  i 2  def 0.3 0.4 0.5 Value Below 0.696 0.4 1.096 0.039 P iddq 0.059 0.032 0.017 Symbol P delta  gd (  0)  def  gd +  def  d 2 P delta 7.3e -4 4.4e -5 1.7e -6 Value Below -2e -4 0.4 0.004 P iddq / P delta 81 721 10000 Dist. Param P  g  def  b  2 Values of P for different  def Values I DDQ  I DDQ 

11 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2211 Example Differential I DDQ Histogram n Better peak resolution with |  I DDQ (i) |, doubles point count

12 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2212  I DDQ Testing Results Item R YL (yield loss ratio) R TE (test escape ratio) P (= R YL + R TE ) Gain in test quality I DDQ 4.4e -4 1.8e -1 P iddq = 1.8e -1  I DDQ 3.5e -3 2.1e -3 P delta = 5.6e -3 P iddq / P delta = 31

13 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2213 I DDQ Built-in Current Testing – Maly and Nigh n Build current sensor into ground bus of device-under-test n Voltage drop device & comparator  Compares virtual ground V GND with V ref at end of each clock – V GND > V ref only in bad circuits  Activates circuit breaker when bad device found

14 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2214 Conceptual BIC Sensor

15 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2215 CMOS BIC Sensor

16 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2216 Setting Optimal # Transistors in Block n Must partition chip into functional units, each with its own BIC  Too large a unit – combined leakage currents erroneously trigger BIC sensor n I defmin – smallest defect current n I noisemax – maximum noise-related peak supply current n Minimum area sensor design at I defmin and I DDQ intersection n N max – maximum # transistors in 1 BIC unit

17 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2217 Graph for Choosing N max

18 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2218 Summary n I DDQ current limit setting to differentiate between good and bad circuits is difficult n I DDQ testing is becoming more problematic  Greater leakage currents in MOSFETs in deep sub-micron technologies  Harder to discriminate elevated I DDQ from 100,000 transistor leakage currents  I DDQ holds promise to alleviate problems n Built-in current testing holds promise


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