1. 1 Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint Seong-Ook Jung, Ki-Wook Kim and Sung-Mo (Steve) Kang DATE’02

2. 2 Outline Introduction Simulation Results on Four Feasible Configuration Dual V t Domino Logic Synthesis Flow Experimental Results Conclusions

3. 3 Introduction Domino logic Clock=0 : precharge Clock=1 : discharge(evaluate) Advantages : high performance Drawback : noise sensitive

4. 4 Introduction noise Solution : increase keeper size Drawbacks : 1. increase power consumption 2. increase evaluation time

5. 5 Introduction V t (threshold voltage) VtVt But exponential increase in subthreshold leakage current(I sub ) of transistors. performance

6. 6 Introduction Tradeoff V t   evaluation time   I sub  keeper size   power consumption   evaluation time  Goal use low v t devices to speedup evaluation while maintaining power consumption and noise constraint.

7. 7 Four Feasible Configuations low v t assignment to NMOS tree and/or PMOS transistor of output inverter.

8. 8 Keeper Sizing for Feasible Configurations Increase keeper size ( width ) to satisfy noise constraint Noise Constraint Topmost NMOS transistors directly connected to 20% of Vdd Other NMOS transistors turn on with Vdd Fail if the output voltage of inverter is greater than 10% of Vdd

9. 9 Keeper Sizing for Feasible Configurations

10. 10 Evaluation Time(t E ) and Power normalized by HH type of each gate with 4:1 P:N ratio output inverter.

11. 11 Power consumption in active mode 1. analyze the simulation result of domino logic gate with 4:1 P:N ratio output inverter. (1) LL type : fastest speed, highest power consumption (2) OR gate : LH slower than HL; Pact of LH greater than HL (3) AND gate : HL slower than LH; Pact is almost the same 2. analyze the effect of up-sizing PMOS transistor from 4:1 to 8:1. t E is improved by increasing the P:N ratio of output inverter (1) OR gate : t E of LL are almost the same (2) OR gate : P act increases (3) AND gate : P act almost the same

12. 12 Leakage current in standby mode normalized by HH type of each gate with 4:1 P:N ratio output inverter. I leak is masured in standby mode by making all logic gates evaluated to reduce leakage I leak is determined by precharge PMOS and NMOS of output inverter (the same size and V t ) I leak is almost the same for all simulation case

13. 13 Dual V t Domino Logic Synthesis Flow

14. 14 Type selection for unmarked logic gates with power constraint (LL, LH and HL type) Dual V t Domino Logic Synthesis Flow For each gate in the critical paths, a proper type is selected for delay minimization with power constraint. Example: OR gate : LL, HL, LH, HH AND gate : LL,LH,HL, HH

15. 15 Dual V t Domino Logic Synthesis Flow Gate selection based on performance sensitivity A gate is chosen such that performance of the gate is maximum.

16. 16 Experimental Results t E - denotes critical path speed-up.(with respect to the initial circuits HH) P act +denotes total active power overhead.(with respect to the initial circuits HH)

17. 17 Experimental Results Bold numbers : maximum speed-up for each benchmark circuit(maximum speed up range from 15.91% to 18.62% with 0.38% to 7.01% active power increase) Half of benchmark circuits achieve around 18% speed-up with less than 1% active power increase The average maximum speed up is 17.43% with 1.84% average active power increase.

18. 18 Conclusions Tradeoffs need to be made among noise, power, and performance. Propose a dual V t synthesis method for high performance with noise (keeper sizing) and power constraint.