1. 24/05/07 A.Masserot - LAPP Annecy1 LAPP R&D – Virgo+ Online architecture T. Bouedo, N.Letendre, A. Masserot, B. Mours, J.M. Nappa, E. Pacaud, S. Vilalte LIGO-G070345-00-Z

2. 24/05/07 A.Masserot - LAPP Annecy2 LAPP R&D – Hardware status

3. 24/05/07 A.Masserot - LAPP Annecy3 New Control and DAQ electronics – Timing system l2 signals distributed overall the ITF:  1PPS(IRIG-B) for the local clock synchronization and the absolute time stamp  A fast clock (10MHz) as centralize fast clock synchronized on the GPS lOptical fibers and differential cables distribution lLinear power supply

4. 24/05/07 A.Masserot - LAPP Annecy4 Atomic GPS receiver lFully tested:  IRIGB frame updated with the GPS and ULeaps fields  No more time stamp errors  1 or 2 jumps of 130ns per week on the 1PPS position in the IRIGB frame l2 others signal generator to purchase: 7-8KEuros per generator lSignal generator SW1050-R-10 from MicroSystems  GPS Motorola M12T receiver  Rubidium clock

5. 24/05/07 A.Masserot - LAPP Annecy5 Timing distribution board lDistribute the timing signals between the buildings and inside a building lPrototype fully tested:  minor modifications on the PCB lPerformances:  Phase jitter between 2 TDBs over 1m of RJ-45 cable: 18,4ps  phase jitter between 2 TDBs over 3Km of fiber : 58.4ps lFirst estimation: 11 TBD A @0.8KEuros – 11 TDB B @1.2KEuros:42.8KEuros

6. 24/05/07 A.Masserot - LAPP Annecy6 ADC board lHigher sampling frequency with embedded shaping/emphasis facilities lADC selection done: AD7674 18bit @ 800kHz l16 differentials channels with analog anti-alias filter at 400KHz lDifferential or single-ended input lDigital anti-alias filters in embedded DSPs( 4 channels per DSP ADPS-21262 @150MHz ) lOn board Timing system to stamp data with the GPS time lCommunication through optic fiber for data transmission and board configuration lFirst estimation: 68 ADC @1.8KEuros : 122.4 KEuros

7. 24/05/07 A.Masserot - LAPP Annecy7 ADC board – ADC selection

8. 24/05/07 A.Masserot - LAPP Annecy8 TOLM board lPrototypes currently used for ADC tests, TOLM /DSP interface tested lUpgrade with 1.6Gbit/s on the optical link and PCI 64bits@66MHz l2 types of TOLM: one as PMC format(v1), one as PC-PCI format(v2) lTOLM Timing jitter: 15ps at the TOLM output – 30ns between two TOLMs with locked oscillator First estimation: 41 TOLM-v1 @0.9KEuros – 35 TOLM-v2 @0.9KEuros: 68KEuros

9. 24/05/07 A.Masserot - LAPP Annecy9 Mux-Demux board lImprove the data access path: optical links router between TOLM interface lElectronic tests ok lFull prototype tests: mid-June 07 lFirst estimation: 32 MUX-DEMUZ @1.6KEuros :51.2KEuros

10. 24/05/07 A.Masserot - LAPP Annecy10 PC server architecture – Linux RTAI lTranstec: dual core opteron @2GHz lKernel tunings: RTAI “vanilla” Linux kernel – Scientific Linux 4 lCPU allocation:  On core involved for real-time operation with the real-time interrupts routed to this CPU only  One core for DAQ and Linux without real-time interrupts routed on it lTest the full Pr and Gc configurations up to 40KHz : maximum expected time: 22us with 14MBytes/s of compressed data

11. 24/05/07 A.Masserot - LAPP Annecy11 Virgo+ Online Architecture

12. 24/05/07 A.Masserot - LAPP Annecy12 PR – GC, QR - GCAli  2x3 channel per longitudinal phD, 2x8 for quadrant  z, d  x, d  y to NE,WE,NI,WI,BS,PR PC Longitudinal + frame builder TOLM DAQ room ADC B7 ADC B8 8 ADCs for longitudinal PhD ADC B1,B1p ADC RFC ADC B2, B2_3f Mux/Demux PC Quadrant + frame builder TOLM 5 ADC for quadrant PhD Mux/Demux to ISYS, OB, SR Mux/Demux ADC B1,B1p ADC B1s,B5,B5_2f ADC B5 ADC B1p ADC B2 ADC B7 ADC B8 Mux/Demux TOLM PC CaRT TOLM

13. 24/05/07 A.Masserot - LAPP Annecy13 ISYS - Proposition To MC PC ISYS control + frame builder TOLM DAQ room ADC quad., SSFS, FMod Mode cleaner building ADC quad. Mux/Demux Laser lab To IB From GC Mux/Demux Could be the same board ADC BMS To BMS lThe PC ISYS runs as ISYS controller

14. 24/05/07 A.Masserot - LAPP Annecy14 Suspension Control (x10) ADC PSD + Coils cur. Coil drivers +DAC & ADC Xx channels Coil drivers +DAC & ADC Xx channels Mux/Demux DSP Control TOLM DSP Damping TOLM PC local control Gx + global ali. TOLM Platform DAQ room Dz or  x,  y Frame building RIO GX TOLM Camera Interface  x,  y dz Daq Room

15. 24/05/07 A.Masserot - LAPP Annecy15 Software lLocking servers:  Scalable architecture to allow the Pr and Gc servers to run on the same or different PCs  Design almost complete  Keep the dictionary for the DAQ collection  Use the dictionary for the pipeline exchange lThe TOLM board is compatible with the RIO PCI architecture  The GxS server will still run on the RIO  The Detection slow control will be done at the first time on the RIO  No DAC with TOLM interface lTiming:  The time stamp is directly available at the TOLM level as GPS time stamp  Push on each input packet by the TOLM (PCI, DSP link)  Timing library will be developed/upgraded

16. 24/05/07 A.Masserot - LAPP Annecy16 Conclusion lTDB production and tests on July-August 2007 lTOLM  v1 production October-November2007  v2 production January-February2008 lMUX-DEMUX production and tests on September-October 2007 lADC  Design complete – First prototype expected the beginning of July2007  Final production foreseen on December2007-Fevrier2008 lTOLM – DSP and Frame Builder : Integration test in September 2007  TOLM driver and libraries for Linux/Linux-RTAI  Dictionary  TOLM Frame builder lTOLM Pr-GC servers: November 2007 lOn site installation: May 2008