1. - 1 - YLD 10/2/99ESINSA Analog IC Design - Filters - Yves Leduc, Advanced System Technology, Wireless Terminals Business Unit Texas Instruments Inc.

2. - 2 - YLD 10/2/99ESINSA Introduction

3. - 3 - YLD 10/2/99ESINSA Analog? Digital? A communication channel can support a digital or an analog signal. By the way, what is an Analog Signal? what is a Digital Signal?

4. - 4 - YLD 10/2/99ESINSA There is obviously a difference: A Hint.

5. - 5 - YLD 10/2/99ESINSA Analog and Digital Signals Too easy But analog and digital signals are sharing the same physical units. Their values are represented by real numbers. The representation of a digital signal is a sequence of integer numbers.

6. - 6 - YLD 10/2/99ESINSA Confused? The confusion exists. The IC design addresses two fields: Physics: the electrical realization. Mathematics: the representation of a signal. We are interested by the electrical realization affecting the representation of the signal.

7. - 7 - YLD 10/2/99ESINSA Analog Signal “The physical values of an analog signal belong to a unique and continuous domain of values.” It does not mean that an analog signal is continuous. It does not mean that an analog circuit must be linear. Signal and noise coexist. 0.00 1.00

8. - 8 - YLD 10/2/99ESINSA Digital Signal “The physical values of a digital signal (when settled) belong to at least two distinctive domains. In each domain, the representation of the signal is unique.” It does not mean that a digital signal has only 2 representations (‘ 0 and 1 ’). The gaps between domains build noise margins. 0 1

9. - 9 - YLD 10/2/99ESINSA An Analog Signal can be translated.offset + in[t] can be amplified.gain * in[t] can be filtered.H[s] * in[s] can be shaped.Min[ in[t], 3.0 ] can be sampled.in[t i ]t i <= t < t i+1 can be quantized.q n q n <= in[t] < q n+1 can be convertednq n <= in[t] < q n+1 can be damaged…  in[t]

10. - 10 - YLD 10/2/99ESINSA A Digital Signal To process correctly a digital signal, a digital circuit must be regenerative, i.e. non linear and active. A digital signal, noisy, distorted or attenuated, must be reshaped. Non linearity provides the necessary discrimination and allows the reshaping of the signal. Amplification is needed to recover from the natural attenuation.

11. - 11 - YLD 10/2/99ESINSA Digital Signal Processing The Digital Signal Processing is based on the mathematical representation of the signal, on an abstraction. A sequence of numbers can be translated, amplified, filtered, shaped, sampled, quantized, converted, and … damaged as an analog signal. The sampled analog signal processing and the digital signal processing are based on the same mathematics. 0.010 0.005 0.015 0.495 0.725 0.780 0.805 0.830 0.855 0.900...

12. - 12 - YLD 10/2/99ESINSA Analog Signal Processing In a Continuous Time Domain. In a Sampled Domain. 0.00 1.00 0.00 1.00

13. - 13 - YLD 10/2/99ESINSA “Mixed Signal Design” 0.00 1.00 0.00 1.00 0.010 0.005 0.015 0.495 0.725 0.780 0.805 0.830 0.855 0.900... Converters, Filters,..

14. - 14 - YLD 10/2/99ESINSA Filtering. At some point in the process of a signal, it is necessary to suppress spurious components. The characteristics of a filter are very depending on the frequency. Filters are implemented in the continuous time or the sampled analog domain, or in the digital domain.  Sampled Analog Domain Digital Domain  Continuous Time Analog Domain

15. - 15 - YLD 10/2/99ESINSA Be consistent. And careful (1). What physical characteristics are coding the representation of the signal? Voltage, Current, Frequency, Phase, Transition,..? Continuous time domain, Sampled domain? Filtering should not damage the representation of the signal.

16. - 16 - YLD 10/2/99ESINSA Be consistent. And careful (2). 0.00 1.00 Is it a sampled signal? Is it a (poor) reconstruction of the sampled signal in the continuous time domain? Passing back and forth from the sampled to the continuous time domain requires specific techniques!

17. - 17 - YLD 10/2/99ESINSA Basic Elements.

18. - 18 - YLD 10/2/99ESINSA Cost. Cost. Cost. Performances are granted. There is a price for the Differentiation. The Cost of Ownership is a major driving factor: BOM (Bill Of Materials) Cost Overhead

19. - 19 - YLD 10/2/99ESINSA Just Cost. Integration is often (*) a solution to meet the cost: it may provide a differentiation it may reduce the BOM it may reduce the cost of the implementation it increase your market shares... (*) ‘often’ does not mean ‘always’

20. - 20 - YLD 10/2/99ESINSA IC elements. Transistors: MOSFET.. Bipolar, JFET  Capacitors:Vertical, Lateral  MOSFET  Resistors:Polysilicon, Bulk Silicon, Metal, ..   MOSFET Inductors:Metal, Bonding Wire  ..    Wires:Several levels of Metal  Pads:Metal 

21. - 21 - YLD 10/2/99ESINSA MOS Transistors. Performances:Speed(digital, analog) Gain, Noise(analog) Factor Of Merit: Gm / Cox(digital, analog) Gm / Gds(analog) Matching(analog) Major ParametersEffective Length Photolithography Process Features Layout Care B DS G

22. - 22 - YLD 10/2/99ESINSA MOS Transistors. Factor of Merit: NMOS / PMOS  3 Minimum Channel Size:  1  m 2 (Idem, low noise input)  100.. 1000  m 2 Gate Oxide:  5.. 10 nm Best Practical Matching:   0.1% Absolute Value Spread:(*) G D S B S G D B (*) sensitive information

23. - 23 - YLD 10/2/99ESINSA Capacitors. Performances:Linearity Matching Memory Effect Factor of Merit:Ceff / Cpar Density (F / m 2 ) Absolute Value Spread Major ParametersDielectric and Dielectric Interface Symmetry Layout Care P2 B P1

24. - 24 - YLD 10/2/99ESINSA Vertical Capacitors Electrodes:Polysilicon, Metal Dielectric: SiO2, Si3N4,.. Factor of Merit: Ceff / Cpar  10 Density:  1 fF /  m 2 Best Practical Matching:   0.1% Absolute Value Spread:   5% Bulk Electrode 2 Electrode 1

25. - 25 - YLD 10/2/99ESINSA Lateral Capacitors Factor of Merit: Ceff / Cpar  (*).. Density:  (*) /  m 2 Best Practical Matching:   (*) % Absolute Value Spread:   (*) % Conventional shape or fractal. (*) no reliable data yet available in the public domain. Bulk Electrode 1 Electrode 2

26. - 26 - YLD 10/2/99ESINSA Resistors. Performances:Voltage Coefficient Temperature Coefficient Matching Factor of Merit:Density (  / m 2 ) Resistance / Parasitic Capacitance Absolute Value Spread Major ParametersPhotolithography Layout Care  B

27. - 27 - YLD 10/2/99ESINSA Polysilicon Resistors Resistivity:20.. 500  /  Best Practical Matching:   0.1 % Absolute Value Spread:   5 % Temperature Coefficient:process dependent Voltage Coefficient:good Bulk

28. - 28 - YLD 10/2/99ESINSA Bulk Resistors Resistivity:1.. 5000  /  Best Practical Matching:   0.1 % Absolute Value Spread:   5 % Voltage Coefficient:fair or poor, process dependent. Temperature Coefficient:process dependent Bulk Doped Area

29. - 29 - YLD 10/2/99ESINSA A Few Sizes MOS Transistor  10  m 2 LNA MOS Transistor  500  m 2 Precision Resistor 1 k  500  m 2 Capacitor 1 pF  1 000  m 2 Bonding Pad  10 000  m 2 Inductor 5 nH  250 000  m 2 Small IC  10 000 000  m 2 Big IC  100 000 000  m 2 [including connections] RC FILTERS

30. - 30 - YLD 10/2/99ESINSA Conclusions Inductors are left for RF designs. External components should be avoided! Integrated R*C is the preferred time constant to build the poles and zeroes of IC filters. MOS transistors are appealing but are intrinsically non linear.

31. - 31 - YLD 10/2/99ESINSA R*C (1) The absolute resistance of an integrated resistor depends on: Material resistivity (doping, granularity,..) Material thickness. (Photolithography) The absolute capacitance of an integrated capacitor depends on: Thickness of the dielectric material. Dielectric constant (Photolithography)

32. - 32 - YLD 10/2/99ESINSA R*C (2) The time constant depends on 2 uncorrelated values: R and C Rwith a sigma of 5% Cwith a sigma of 5% It is impossible to rely on R*C to build accurate filters at a correct cost. So what?

33. - 33 - YLD 10/2/99ESINSA Exercise 1 Optimize  = R * C