1. Micro transductors ’08 Low Leakage VLSI Design Dr.-Ing. Frank Sill Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil franksill@ufmg.br http://www.cpdee.ufmg.br/~frank/

2. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 2 Agenda Recap Trends Leakage components Leakage reduction  On technology level  On transistor and gate level  On architecture level

3. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 3 Recap: Problems of Power Dissipation Continuously increasing performance demands  Increasing power dissipation of technical devices  Today: power dissipation is a main problem High Power dissipation leads to:  High efforts for cooling  Increasing operational costs  Reduced reliability  High efforts for cooling  Increasing operational costs  Reduced reliability  Reduced time of operation  Higher weight (batteries)  Reduced mobility  Reduced time of operation  Higher weight (batteries)  Reduced mobility

4. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 4 Most popular method for power reduction of clock signals and functional units Gate off clock to idle functional units Logic for generation of disable signal necessary  Higher complexity of control logic  Higher power consumption  Critical timing critical for avoiding of clock glitches at OR gate output  Additional gate delay on clock signal Recap: Clock Gating RegReg clock disable Functional unit Source: Irwin, 2000

5. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 5 Recap: Parallel Architecture Comb. Logic Copy 1 Comb. Logic Copy 2 Comb. Logic Copy N Register N to 1 multiplexer Multiphase Clock gen. and mux control Input Output CK f clk f clk /N Each copy processes every Nth input, operates at reduced voltage Supply voltage: V N ≤ V ref N = Deg. of parallelism Source: Agarwal, 2007 f clk /N

6. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 6 Data Recap: Pipelined Architecture Reduces the propagation time of a block by factor N  Voltage can be reduced at constant clock frequency Constant throughput Functionality: CLK Area A CLK A/N

7. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 7 Recap: Busses Shared Bus B B Segmented Bus Source: Evgeny Bolotin – Jan 2004 Bus segmentation  Another way to reduce shared buses  Control of bus segment by controller blocks (B)

8. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 8 Recap: Adaptive DVS Speed Time T1T2T1T2 Idle Same work, lower energy Task Task with 100 ms deadline, requires 50 ms CPU time at full speed  Normal system gives 50 ms computation, 50 ms idle/stopped time  Half speed/voltage system gives 100 ms computation, 0 ms idle  Same number of CPU cycles but: E = C (V DD /2) 2 = E ref / 4  Dynamic Voltage Scaling adapts voltage to workload Time

9. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 9 Recap: Processor Modes Source: Transmeta

10. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 10 Battery aware design 1000 mAh (Standard Capacity) Discharge current (mA) Capacity (mAh) ( Rated Current) 125mA 1000 800 600 400 200 Available Charge (mA) time idle Discharge Current (mA) time Non-linear effects influence life time of batteries “Rate Capacity”  If discharging currents higher than allowed  real capacity goes under nominal capacity “Battery Recovery”  Pulsed discharge increases nominal capacity  Based on recovery times  (as long there is no rate capacity effect) Source: Timmermann, 2007

11. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 11 Si Substrate Metal Gate High-k Tri-Gate S G D III-V S Carbon Nanotube FET 50 nm 35 nm 30 nm SiGe S/D Strained Silicon SiGe S/D Strained Silicon 90 nm65 nm45 nm32 nm 20042006200820102012+ Technology Generation 20 nm 10 nm 5 nm Nanowire Manufacturing Development Research Trends

12. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 12 Trends cont‘d Dynamic Power Dissipation Power Dissipation by Leakage currents Source: S. Borkar (Intel), ‘05

13. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 13 Recap: Transistor Geometrics n+ p-type body polysilicon gate Gate length L Source: Rabaey,“Digital Integrated Circuits”,1995 Gate-width W SiO 2 gate oxide (good insulator, e ox = 3.9 t ox – thickness of oxide layer t ox

14. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 14 Subthreshold Leakage Threshold Voltage  Transistor characteristic  If: „Gate-Source“-Voltage V gs higher than V th  Channel under Gate  Current between Drain and Source  If: V gs lower than V th  (ideal) No current Subthreshold leakage I sub  Leakage between Drain and Source when V gs < V th  Based on: Short Channels Diffusion Thermionic Emission Source Drain Gate I sub

15. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 15 Subthreshold Leakage cont’d 0V th ’V th Log (Drain current) Gate voltage Short-channel device I sub Source: Agarwal, 2007 Transistor is conducting NMOS-Transistor

16. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 16 Temperature dependence I OFF at 110 0 C I sub at 25 0 C 130nm  6x  70nm  16x  Based on Thermionic Emission: subthreshold leakage I sub increases with temperature Source: Chatterjee, Intel-labs

17. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 17 Gate Oxide Leakage I gate Tunneling effect  Electromagnetic wave strike at barrier:  Reflection + Intrusion into barrier  If thickness is small enough:  Wave interfuse barrier partially: (Electrons tunnel through Barrier) Gate oxide leakage I gate  In Nanometer-Transistors, where T ox < 2 nm  Electrons tunnel through gate oxide  Leakage current

18. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 18 Gate Oxide Thickness at 45 nm

19. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 19 Gate Oxide Leakage cont’d Components of Gate Oxide Leakage:  Tunneling currents through overlap regions (gate-drain I gso, gate- source I gdo )  Tunneling currents into channel (gate-drain I gis, gate-source I gcd )  Tunneling currents between gate and bulk (I gb )

20. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 20 Drain Induced Barrier Lowering (DIBL) Electrons have to overcome potential barrier to enter the channel Ideal: Potential barrier is only controlled by gate voltage Changed by gate voltage V gs < V th V gs > V th Height of curve = Potential barrier

21. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 21 Drain Induced Barrier Lowering cont’d At short channel transistors potential barrier is also affected by drain voltage  If V ds = V DD Transistors can start to conduct even if V gs < V th Short-channel transistor (L < 180 nm) Long-channel transistor (L > 2 µm) Lowering of potential barrier

22. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 22 Further Leakage Components Reverse bias pn junction conduction I pn Gate induced drain leakage I GIDL Drain source punchthrough I PT Hot carrier injection I HCI I HCI I pt I GIDL I pn

23. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 23 Leakage Dependencies Leakage depends on:  Gate Width (I sub, I gate )  Gate Length (I sub )  Gate Oxide Thickness (I gate )  Threshold Voltage (I sub )  Temperature (I sub )  Input state (I gate )

24. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 24 Recap: Levels of Optimization nach Massoud Pedram

25. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 25 Approaches to Reduce Leakage Idle states (passive) Components have nothing to do Active states Components are working Approaches for different states

26. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 26 Approaches on Technology Level Retrograde well Different Concentration of dopant (implanted) inside the substrat Lowest concentration: near the channel  Lower subthreshold leakage Highest concentration: near the bulk connection  Reduced possibility for punch- through

27. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 27 Approaches on Technology Level cont’d  Halo Implants  High doped regions near source and drain areas  Reduced Drain Induced Barrier Lowering  Offset Spacer  Silicon nitride placed beside gate area  Reduced overlap regions  Reduced gate leakage through overlap regions  But: Increased channel resistance

28. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 28 Power & Delay Dependence of V th w.o. gate leakage Source: Sakurai, ‘01

29. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 29 Influence of Threshold Voltage V th Threshold Voltage V th :  Influence on sub-threshold leakage I sub  Influence on delay of logic gates I sub Delay

30. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 30 Influence of Gate Oxide Thickness T ox Gate oxide Thickness T ox :  Influence on gate oxide leakage I gate  Influence on delay I gate Delay

31. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 31 Recap: Data Paths Data propagate through different data paths between registers (flipflops - FF) Paths mostly differ in propagation delay times Frequency of clock signal (CLK) depends on path with longest delay  critical path Paths Path

32. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 32 Recap: Slack B A Y C time all Inputs of G1 arrived G1 ready with evaluation delay of G1 all inputs of G2 arrived Slack for G1

33. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 33 Dual-V th / Dual-T ox Two different gate types:  Gates consist of „low-V th “- or „low-T ox “-transistors  Low threshold voltage or thin gate oxide layer  For critical paths  High leakage  Gates consist of „low-V th “- or „low-T ox “-transistors  Low threshold voltage or thin gate oxide layer  For critical paths  High leakage “LVT / LTO”-Gates  Gate consist of „high-V th “- „high-T ox “-transistors  High threshold voltage or thick gate oxide layer  For uncritical paths  Low leakage  Gate consist of „high-V th “- „high-T ox “-transistors  High threshold voltage or thick gate oxide layer  For uncritical paths  Low leakage “HVT / HTO”-Gate  Leakage reduction at constant performance (no level converter necessary)

34. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 34 Performance at different Dual-V th Measured at NAND2 BPTM 65nm Technology

35. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 35 Leakage I sub at different Dual-V th Measured at NAND2 BPTM 65nm Technology

36. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 36 Dual-V th / Dual-T ox Example Critical Path HVT-or HTO-Gates LVT-or LTO-Gates

37. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 37 Dual-V th / Dual-T ox at Transistor Level  Better leakage reduction possible  Much higher effort in design phase Uncritical path Critical path “low-V th ” or “low-T ox ” transistors “high-V th ” or “high-T ox ” transistors

38. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 38 Simultaneous V t, Size and V dd Assignment Leakage reduced through either increasing V th or lowering V DD  Lowering V dd also reduces dynamic power Topological constraints on V DD assignment  Requires use of voltage level converters Assign V DD first then perform sizing/V th assignment Topology Based Slack Distribution Change V DD of Gates with Sufficient Slack Begin Delay Minimize All Paths Sensitivity Based Slack Distribution Change Gates With Sufficient Slack P  P   End Source: [Nguyen, et al., ISLPED03]

39. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 39 Stack Effect Transistor stack: at least two transistor from same type (NMOS or PMOS) in a row Based on behavior of internal nodes:  The more transistors are non-conducting (off) the lower the leakage Source: Roy, “Lecture”

40. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 40 Sleep Transistors  Idea: Insertion of additional transistors between logic block and supply lines  This transistors: connect with SLEEP- signal  If circuit has nothing to do:  SLEEP signal is active: Stack effect (additional off transistor in row to other)  If sleep transistors are High-V th : approach also called Multi-Threshold CMOS (MTCMOS)  Mostly insertion only of 1 Transistor Low-V th logic cells Vss Vdd sleep Virtual Vss Virtual Vdd sleep Source: Kaijian Shi, Synopsys

41. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 41 Sleep Transistors: Realization VDD Global VDD V VDD1 domain Ring style sleep transistor implementation Sleep transistors are placed around each VVDD island V VDD2 domain Source: Kaijian Shi, Synopsys

42. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 42 Sleep Transistors: Realization cont’d Grid style sleep transistor implementation Source: Kaijian Shi, Synopsys Global VDD V VDD2 VDD VVDD1 V VDD2 V DD network cross chip; V VDD networks in each gating domain Sleep transistors are placed in grid connecting V DD and V VDDs

43. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 43 Sleep Transistors: Problems Sleep transistor can be modeled as resistor R In active mode (gate is working)  Current I through sleep transistor  Voltage V x drop over resistor  Output voltage reduced to V DD -V x Reduced Delay (of following blocks) Current I is not leakage current! I is discharging current of load capacitance

44. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 44 Stackforcing Simple method of using stack effect  Increasing stack by splitting transistors  C in stays constant  Only one technology is needed  Area is (almost) the same  Drive strength (drain-source current) is reduced  delay goes down

45. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 45 Stackforcing cont’d Source: Narendra, et al., ISLPED01 Normalized I sub Normalized delay No Stackforcing

46. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 46 Input Vector Control (IVC) Leakage of gate depends on input vector

47. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 47 Every circuits is input vector with minimum leakage Idea: If design is in passive mode  SLEEP signal gets active  Sleep vector is applied Input Vector Control cont’d

48. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 48 Pin Reordering Gate Leakage in stack depends on input vector Same logic input vector (amounts of ‘0’ and ‘1’ is equal) → can result in different leakage If input probability is know  reorder pins so that highest probable state has minimum gate leakage BPTM, 65 nm technology

49. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 49 Threshold voltage V th depends on bulk voltage (V bs ) As leakage (I sub ) and delay depends on V th  Delay and leakage (I sub ) can be controlled over V bs VTCMOS: dynamic adjustment of frequency and V th through back- gate bias (=V bs ) control 5 8 1 2 3 4 5 -1,5 -0,5 00,5 Back-gate Bias V BS [V] leakage power delay normalized power normalized delay Variable Threshold CMOS (VTCMOS)

50. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 50 VTCMOS: V TH -hopping scheme V th - controller Frequency - controller V DD GND V BSP1 V BSP V BSP2 V BSH1 V BSH2 V BSH Target ProcessorV th - Selector f clk1 or f clk2 Power Control Block V th_high _enable V th_low _enable Source: NOSE et al.: - V TH HOPPING SCHEME

51. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 51 Voltage islands Level converter (Processor)

52. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 52 Comparison of Approaches ApproachLevelModeProsCons retrograde wellTechnology active / passive ↓I pt Technology++ Halo-ImplantsTechnology active / passive ↓DIBLTechnology++ Offset spacerTechnology active / passive ↓I gate ↑t d, Technology++ Sleep transistorsGate / Systempassive↓↓ I sub ↑td↑td + IVCAlgorithmpassive↓I gate, ↓I sub -+

53. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 53 Comparison of Approaches cont’d ApproachLevelModeProsCons DVTCMOSTransistor / Gate active / passive ↓I sub Technology+ DTOCMOSTransistor / Gate active / passive ↓I gate Technology+ Stack forcingTransistor active / passive ↓I sub ↑td↑td o VTCMOSSystem passive / slow ↓I sub Routing+ DVSSystem passive / slow ↓I gate, ↓ I sub -+ DVDDGate active / passive ↓I gate, ↓I sub Converter, Routing + Voltage islandsArchitecture passive / slow ↓I gate, ↓I sub Converter+

54. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 54 Backup

55. Copyright Sill, 2008 Micro transductors ‘08, Low Leakage 55 Stack Effect