1. Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer Systems Presentation at Intel June 16th, 2000

2. Talk at Intel, Dirk Stroobandt 2 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit characterization Conclusions Outline

3. June 16th, 2000Talk at Intel, Dirk Stroobandt 3 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit characterization Conclusions Outline

4. June 16th, 2000Talk at Intel, Dirk Stroobandt 4 Importance of wires increases (they do not scale as components). For future designs, very little is known. Roadmapping uses a priori estimation techniques. To improve CAD tools for design layout generation. CAD tools have to take into account: timing constraints, area constraints, performance, power dissipation… All these constraints: wires should be as short as possible. Estimation at early stage aids the CAD tools in finding a better solution through fewer design cycle iterations. Why do we need a priori interconnect prediction?

5. June 16th, 2000Talk at Intel, Dirk Stroobandt 5 Why do we need a priori interconnect prediction? To evaluate new computer architectures To adhere to the increasing performance demands, new computer architectures are needed. Each of them must be evaluated thoroughly. A priori estimates immediately provide a ground for drawing preliminary conclusions. Different architectures can be compared to each other. Applications for evaluating three-dimensional (opto- electronic) architectures, FPGA’s, MCM’s,...

6. June 16th, 2000Talk at Intel, Dirk Stroobandt 6 Components of the physical design step layout Layout generation circuitarchitecture

7. June 16th, 2000Talk at Intel, Dirk Stroobandt 7 Net External net Internal net Logic block Multi-terminal nets have a net degree > 2 Circuit model Terminal / pin

8. June 16th, 2000Talk at Intel, Dirk Stroobandt 8 8 nets cut 4 nets cut Model for partitioning Optimal partitioning: minimal number of nets cut

9. June 16th, 2000Talk at Intel, Dirk Stroobandt 9 Model for partitioning Module New net New terminal

10. June 16th, 2000Talk at Intel, Dirk Stroobandt 10 The three basic models Circuit model Placement and routing model Model for the architecture Pad Channel Manhattan grid using Manhattan metric Cell

11. June 16th, 2000Talk at Intel, Dirk Stroobandt 11 The three basic models Optimal routing = routing through shortest path requires channels with sufficiently high density (or: enough routing layers) for multi-terminal nets: Steiner trees This defines the net length for known endpoints Placement and routing model Optimal placement = placement with minimal total wire length over all possible placements.

12. June 16th, 2000Talk at Intel, Dirk Stroobandt 12 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit characterization Conclusions Outline

13. June 16th, 2000Talk at Intel, Dirk Stroobandt 13 T = t B p 1 1 100010 100 T B Rent’s rule average Rent’s rule (simple) 0  p  1 (complex) Normal values: 0.5  p  0.75 Measure for the complexity of the interconnection topology p = Rent exponent Rent’s rule was first described by [Landman and Russo, 1971] For average number of terminals and blocks per module: t = average # term./block

14. June 16th, 2000Talk at Intel, Dirk Stroobandt 14 BB TT If  B cells are added, what is the increase  T? In the absence of any other information we guess Overestimate: many of  T terminals connect to T terminals and so do not contribute to the total. We introduce a factor p (p <1) which indicates how self connected the netlist is Or, if  B &  T are small compared to B and T Statistically homogenous system T B Rent’s rule

15. June 16th, 2000Talk at Intel, Dirk Stroobandt 15 Rent’s rule average Rent’s rule Rent’s rule is experimentally validated for a lot of real circuits and for different partitioning methodologies. T = t B p Distinguish between: p* : intrinsic Rent exponent p : Rent exponent for a given placement p’ : Rent exponent for a given partitioning Deviation for high B and T: Rent’s region II (cfr. later).

16. June 16th, 2000Talk at Intel, Dirk Stroobandt 16 Rent’s rule Rent’s rule is a result of the self-similarity within circuits Assumption: interconnection complexity is equal at all levels.

17. June 16th, 2000Talk at Intel, Dirk Stroobandt 17 Extension: the local Rent exponent Variations in Rent’s rule: global variations (e.g., lower complexity after Technology mapping of the circuit, duplication); local variations. Two kinds of local variations in Rent’s rule: hierarchical locality: some hierarchical levels are more complex than others; spatial locality: some circuit parts are more complex than others. Both are deviations from Rent’s rule that can be modelled well.

18. June 16th, 2000Talk at Intel, Dirk Stroobandt 18 Hierarchical locality: Rent’s region II Causes of region II: - pin limitation problem; - parallel to serial (complexity is moved from space to time, number of pins is lowered); - coding (input and output stream compact). average Rent’s rule

19. June 16th, 2000Talk at Intel, Dirk Stroobandt 19 Hierarchical locality: region III For some circuits: also deviation at low end [Stroobandt, GLSVLSI 99]. Mismatch between the available (library) and the desired (design) complexity of interconnect topology. Only for circuits with logic blocks that have many inputs. T

20. June 16th, 2000Talk at Intel, Dirk Stroobandt 20 Hierarchical locality: modelling Use incremental Rent exponent (proportional to the slope of Rent’s curve in a single point) [Van Marck et al., ISYCS 1995].

21. June 16th, 2000Talk at Intel, Dirk Stroobandt 21 Spatial locality in Rent’s rule Inhomogeneous circuits: different parts have different interconnection complexity. For separate parts: Only one Rent exponent (heterogeneous) might not be realistic. Clustering: simple parts will be absorbed by complex parts.

22. June 16th, 2000Talk at Intel, Dirk Stroobandt 22 Local Rent exponent Higher partitioning levels: Rent exponents will merge. Spreading of the values with steep slope (decreasing) for complex part and gentle slope (increasing) for simple part. Local Rent exponent tangent slope of the line that combines all partitions containing the local block(s). T B 1 1 1 1 1 1 2 2 2 2 2 2

23. June 16th, 2000Talk at Intel, Dirk Stroobandt 23 Heterogeneous Rent’s rule Suggested by [Zarkesh-Ha, Davis, Loh, and Meindl,’98] Weighted arithmetic average of the logarithm of T: Heterogeneous Rent’s rule (for 2 parts):

24. June 16th, 2000Talk at Intel, Dirk Stroobandt 24 Use of Rent’s rule in CAD Rent’s rule is very powerful as a measure of the complexity of the interconnection topology Can aid in the partitioning process Benchmark generators are based on Rent’s rule Is basis for a priori estimates in CAD

25. June 16th, 2000Talk at Intel, Dirk Stroobandt 25 Rent’s rule in partitioning Actual goal: minimize the number of pins per module. We should use a pin count criterion. External multi-terminal nets lead to only one new pin instead of two when cut. Preferring external nets to be cut will better keep clusters together.

26. June 16th, 2000Talk at Intel, Dirk Stroobandt 26 Rent’s rule in partitioning Solution: use a new ratio value (in ratiocut partitioning) based on terminal count [Stroobandt, ISCAS’99]: Better partitions are obtained because the total number of pins for each module is taken into account by the cost function.

27. June 16th, 2000Talk at Intel, Dirk Stroobandt 27 Rent’s rule in partitioning Better (ratio cut) heuristic by using terminal count prediction [Stroobandt, ISCAS‘99]. Clustering property of the ratio cut: use Rent’s rule instead of uniformly distributed random graph. New ratio: Instead of old ratio:

28. June 16th, 2000Talk at Intel, Dirk Stroobandt 28 Rent’s rule in partitioning Important (especially in pin-limited designs): terminal balancing [Stroobandt, Swiss CAD/CAM‘99]. Minimizing the terminal count alone is not enough. Additional cost function for terminal balancing: Terminal

29. June 16th, 2000Talk at Intel, Dirk Stroobandt 29 Rent’s rule in benchmark generation Generating benchmarks in a hierarchical way Rent’s rule is used for estimating the number of connections Other parameters have to be controlled as well: –Classical parameters: *total number of gates *total number of nets *total number of pins –Gate terminal distribution –Net degree distribution Other issues: gate functionality, redundancy, timing constraints,...

30. June 16th, 2000Talk at Intel, Dirk Stroobandt 30 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit characterization Conclusions Outline

31. June 16th, 2000Talk at Intel, Dirk Stroobandt 31 1. Partition the circuit into 4 modules of equal size such that Rent’s rule applies (minimal number of pins). 2. Partition the Manhattan grid in 4 subgrids of equal size in a symmetrical way. Donath’s hierarchical placement model

32. June 16th, 2000Talk at Intel, Dirk Stroobandt 32 3. Each subcircuit (module) is mapped to a subgrid. 4. Repeat recursively until all logic blocks are assigned to exactly one grid cell in the Manhattan grid. Donath’s hierarchical placement model mapping

33. June 16th, 2000Talk at Intel, Dirk Stroobandt 33 Donath’s length estimation model At each level: Rent’s rule gives number of connections number of terminals per module directly from Rent’s rule (partitioning based Rent exponent p’); every net not cut before (internal net): 2 new terminals; every net previously cut (external net): 1 new terminal; assumption: ratio f = (#internal nets)/(#nets cut) is constant over all levels k [Stroobandt and Kurdahi, GLSVLSI’98]; number of nets cut at level k (N k ) equals where  =1/(1+f);  depends on the total number of nets in the circuit and is bounded by 0.5 and 1.

34. June 16th, 2000Talk at Intel, Dirk Stroobandt 34 Donath’s length estimation model Length of the connections at level k ? Donath assumes: all connection source and destination cells are uniformly distributed over the grid. Adjacent ( A -) combination Diagonal ( D -) combination

35. June 16th, 2000Talk at Intel, Dirk Stroobandt 35 Number of connections at level k: Average length A -combination: Average length D -combination: Average length level k: Total average length: with and 2 K = G = total number of gates Average interconnection length

36. June 16th, 2000Talk at Intel, Dirk Stroobandt 36 Results Donath Scaling of the average length L as a function of the number of logic blocks G : L G 0 5 10 15 20 25 30 11010010 3 10 6 10 5 10 4 10 7 p = 0.7 p = 0.5 p = 0.3 Similar to measurements on placed designs.

37. June 16th, 2000Talk at Intel, Dirk Stroobandt 37 Results Donath Theoretical average wire length too high by a factor 2 10000 L G 1 2 3 4 6 5 7 101001000 8 experiment theory 0

38. June 16th, 2000Talk at Intel, Dirk Stroobandt 38 Enumeration: site density function (only architecture dependent). Occupying probability favours short interconnections (for an optimal placement) (darker) Keep wire length scaling by hierarchical placement. Improve on uniform probability for all connections at one level (not a good model for an optimal placement). Including optimal placement model

39. June 16th, 2000Talk at Intel, Dirk Stroobandt 39 Including optimal placement model Wirelength distributions contain two parts: site density function and probability distribution all possibilities requires enumeration (use generating polynomials, [Stroobandt & Van Marck, SLIP2000] ) probability of occurrence shorter wires more probable [Stroobandt, VLSI Design vol. 10, 1999]

40. June 16th, 2000Talk at Intel, Dirk Stroobandt 40 Wire length distribution From this we can deduct that For short lengths: Local distributions at each level have similar shapes (self-similarity)  peak values scale. Integral of local distributions equals number of connections. Global distribution follows peaks.

41. June 16th, 2000Talk at Intel, Dirk Stroobandt 41 Occupying probability: results 8 Occupying prob. 10000 L G 1 2 3 4 6 5 7 101001000 0 Donath experiment Use probability on each hierarchical level (local distributions).

42. June 16th, 2000Talk at Intel, Dirk Stroobandt 42 Occupying probability: results Effect of the occupying probability: boosting the local wire length distributions (per level) for short wire lengths Occupying prob. 100 Wire length percent of wires 10 1 0,1 0,01 10 -3 10 -4 100001101001000 per level total global trend Donath 1 Wire length 101001000 per level total global trend 10000

43. June 16th, 2000Talk at Intel, Dirk Stroobandt 43 Effect of the occupying probability on the total distribution: more short wires = less long wires  average wire length is shorter Occupying probability: results 100 10 1 10 -1 10 -2 10 -3 10 -4 10 -5 110100100010000 Wire length percent wires Occupying prob. Donath

44. June 16th, 2000Talk at Intel, Dirk Stroobandt 44 Occupying probability: results 10 20 30 40 50 60 110 Wire length Percent wires Occupying prob. Donath 2 345678 9 global trend -23% -8% +10% +6%

45. June 16th, 2000Talk at Intel, Dirk Stroobandt 45 Occupying probability: results 0,1 1 10 100 1000 1100 Wire length Number of wires Occupying prob. Donath measurement 10

46. June 16th, 2000Talk at Intel, Dirk Stroobandt 46 Davis’ probability function Introduced by [Davis, De, and Meindl, IEEE T El. Dev., ‘98]. Number of interconnections at distance l is calculated for every gate separately, using Rent’s rule. Three regions: gate under investigation (A), target gates (C), and gates in between (B). Number of connections between A and C is calculated. This approach alleviates the discrete effects at the boundaries of the hierarchical levels while maintaining the scaling behaviour.

47. June 16th, 2000Talk at Intel, Dirk Stroobandt 47 Davis’ probability function B B BB BB B ABB BB B C C C C C C C C C C C C C BA C BA C BA C BA C BA =+-- TACTAC TABTAB T BC TBTB T ABC = +-- Assumption: net cannot connect A,B, and C

48. June 16th, 2000Talk at Intel, Dirk Stroobandt 48 Davis’ probability function B B BB BB B ABB BB B C C C C C C C C C C C C For cells placed in infinite 2D plane

49. June 16th, 2000Talk at Intel, Dirk Stroobandt 49 Planar wirelength model A L L Finite system, B tot =L 2, no edges, approximate form for q(l) 28

50. June 16th, 2000Talk at Intel, Dirk Stroobandt 50 Planar wirelength model B (Davis) L L Finite system, B tot =L 2, includes edge effects, use q(l) 29

51. June 16th, 2000Talk at Intel, Dirk Stroobandt 51 Planar wirelength model comparison Model A Model B B tot = 1024 p = 0.66 Model A: L av = 4.53 Model B: L av = 2.27 30

52. June 16th, 2000Talk at Intel, Dirk Stroobandt 52 Relationship between models from Davis (planar model B) and Stroobandt (hierarchical model C) D c (l,h) D b (l) same q’(l) essentially identical!

53. June 16th, 2000Talk at Intel, Dirk Stroobandt 53 Hierarchical wirelength model comparison Model D Model C C tot = 1024 p = 0.66 Model C (Stroobandt): L av = 2.05 Model D (Donath): L av = 5.14 Model C: q(l) and hierarchy Model D: only hierarchy (q(l)=1)

54. June 16th, 2000Talk at Intel, Dirk Stroobandt 54 Planar and hierarchical model comparison Model D Model C Model A Model B Models B (planar) and C (hierarchical ) are equivalent if the Rent exponent used for the probability function (depends on placement) and the one used for the number of nets per hierarchical level (based on partitioning) are the same

55. June 16th, 2000Talk at Intel, Dirk Stroobandt 55 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit Characterization Conclusions Outline

56. June 16th, 2000Talk at Intel, Dirk Stroobandt 56 Extension to three-dimensional grids

57. June 16th, 2000Talk at Intel, Dirk Stroobandt 57 Anisotropic systems

58. June 16th, 2000Talk at Intel, Dirk Stroobandt 58 Anisotropic systems Basic method: Donath’s method in 3D Not all dimensions are equal (e.g., optical links in 3rd D) possibly larger latency of the optical link (compared to intra- chip connection); influence of the spacing of the optical links across the area (detours may have to be made); limitation of number of optical layers Introducing an optical cost

59. June 16th, 2000Talk at Intel, Dirk Stroobandt 59 Anisotropic systems If limited number of layers: use third dimension for topmost hierarchical levels (fewest interconnections). For lower levels: 2D method. 2D and 1D partitioning are sometimes used to get closer to the (optimal in isotropic grids) cubic form. Depending on the optical cost, it is advantageous either to strive for getting to the electrical plains as soon as possible (high optical cost, use at high levels only) or to partition the electrical planes first (low optical cost).

60. June 16th, 2000Talk at Intel, Dirk Stroobandt 60 External nets Importance of good wire length estimates for external nets during the placement process: For highly pin-limited designs: placement will be in a ring-shaped fashion (along the border of the chip).

61. June 16th, 2000Talk at Intel, Dirk Stroobandt 61 Wire lengths at system level At system level: many long wires (peak in distribution). How to model these? Davis and Meindl ‘98: estimation based on Rent’s rule with the floorplanning blocks as logic blocks. IMPORTANT!

62. June 16th, 2000Talk at Intel, Dirk Stroobandt 62 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit characterization Conclusions Outline

63. June 16th, 2000Talk at Intel, Dirk Stroobandt 63 Improving CAD tools for design layout Digital design is complex Computer-aided design (CAD) More efficient layout generation requires good wire length estimates. Layer assignment in routing effects of vias, blockages congestion,... A priori estimates are rough but can already provide us with a lot of information.

64. June 16th, 2000Talk at Intel, Dirk Stroobandt 64 Evaluating new computer architectures Estimation for evaluating and comparing different architectures Circuit characterization We need parameters to classify circuits in classes and to optimize them. Benchmark generation based on Rent’s rule.

65. June 16th, 2000Talk at Intel, Dirk Stroobandt 65 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit Characterization Conclusions Outline

66. June 16th, 2000Talk at Intel, Dirk Stroobandt 66 Technology extrapolation Evaluates impact of design technology process technology Evaluates impact on achievable design associated design problems Questions to be addressed Sets new requirements for CAD tools and methodologies Roadmaps: familiar and influential example How and when do L, SOI, SER, etc. matter? What is the most power-efficient noise management strategy? Will layout tools need to perform process simulation to efficiently model cross-die and cross-wafer manufacturing variation?

67. June 16th, 2000Talk at Intel, Dirk Stroobandt 67 Current extrapolation systems Previous and ongoing efforts ITRS Roadmaps Tools: SUSPENS, GENESYS, RIPE, BACPAC, … Numerous tools in industry Use models for delay power architecture wirelength estimation...

68. June 16th, 2000Talk at Intel, Dirk Stroobandt 68 GTX: GSRC technology extrapolation system GTX is set up as a framework for technology extrapolation [Caldwell et al., DAC 2000] Parameters (data) Rules (models) Rule chain (study) Knowledge Engine (derivation) GUI (presentation) Implementation User inputs Pre-packaged GTX

69. June 16th, 2000Talk at Intel, Dirk Stroobandt 69 GTX Check it out at http://vlsicad.cs.ucla.edu/GSRC/GTX/

70. June 16th, 2000Talk at Intel, Dirk Stroobandt 70 wirelength estimation models (Donath, …) actual placement information Models of achievable routing Required versus available resources

71. June 16th, 2000Talk at Intel, Dirk Stroobandt 71 Models of achievable routing Required versus available resources limited by routing efficiency factor  r

72. June 16th, 2000Talk at Intel, Dirk Stroobandt 72 Models of achievable routing Required versus available resources limited by power/ground (signal net fraction s i )

73. June 16th, 2000Talk at Intel, Dirk Stroobandt 73 Models of achievable routing Required versus available resources limited by via impact factor v i (ripple effect) utilization factor U i (available / supplied area)

74. June 16th, 2000Talk at Intel, Dirk Stroobandt 74 Use of achievable routing models Optimizing interconnect process parameters for future designs (number of layers, wire width and pitch per layer,...) With given layer characteristics: predict the number of layers needed If number of layers fixed: oracle “(not) routable!” (SUSPENS, GENESYS, RIPE, BACPAC, GTX) Supplying objectives that guide layout tools to promising solutions (wire planning) [Kahng, Mantik and Stroobandt, ISPD 2000]

75. June 16th, 2000Talk at Intel, Dirk Stroobandt 75 Layer assignment in routing DSM design routing tools have to account for delay constraints yield power … Conventional technique: router assigns wires to layers wire sizing, repeater insertion/sizing applied More interesting approach: wire sizing etc. used by router to assign wires [Kahng and Stroobandt, SLIP 2000]

76. June 16th, 2000Talk at Intel, Dirk Stroobandt 76 Our Layer Assignment Concept Search for optimal layer for a wire with optimal wire size, number and size of repeaters for each wire meeting consistent stage delay constraints taking total repeater area constraint into account accounting for impact of vias A priori estimation techniques make it useful for application both before / after placement Potential applications improving CAD layout tools studying effects of technological parameters optimizing fabrication process

77. June 16th, 2000Talk at Intel, Dirk Stroobandt 77 Problem and Models Optimization objective: # of layers needed Degrees of freedom (for each wire) choice of layer parameters wire width number of repeaters size of the repeaters Find the optimal assignment of wires to wiring layers subject to delay constraints and total repeater area constraints

78. June 16th, 2000Talk at Intel, Dirk Stroobandt 78 Layer Assignment method 2 phases: optimize, then round to integers Phase 1: Calculate minimal delay T min. T min <T target ? A min <A limit ? Sort costs in increasing order. Repeat for all wires.  C min < 0? Calculate cost  C for moving wire to other tier while optimizing W, N r. Calculate minimal repeater area A min. Y T target =T min. N A limit =A min Solution found! N Solution found! N Move K wires with smallest  C<0. Repeat. Y Create initial solution on “fattest” tier. Y

79. June 16th, 2000Talk at Intel, Dirk Stroobandt 79 A Typical Example Tier type 2 Tier type 1 Tier type 0 Wirelength (mm) Delay (ps) Wire width (  m) 02400224Number of repeaters

80. June 16th, 2000Talk at Intel, Dirk Stroobandt 80 Target Delay Influence Tier type 2 Tier type 1 Tier type 0 Wirelength (mm) Delay (ps) Wire width (  m) Wirelength (mm)

81. June 16th, 2000Talk at Intel, Dirk Stroobandt 81 Uniform Versus Non-uniform Stacks 6.3134 7.1053 Tier 2 Tier 1 Tier 0 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Number of layers per tier type 8.0251 Total

82. June 16th, 2000Talk at Intel, Dirk Stroobandt 82 Optimal Layer Stack Monotonic? 5.4426 7.0002 19.3665 Tier 2 Tier 1 Tier 0 7.1285 20 18 16 14 12 10 8 6 4 2 0 Number of layers per tier type 20 18 16 14 12 10 8 6 4 2 0

83. June 16th, 2000Talk at Intel, Dirk Stroobandt 83 Why do we need a priori interconnect prediction? Basic models Rent’s rule with extensions and applications A priori wirelength prediction New evolutions Applications CAD (extrapolation, achievable routing, layer assignment) Evaluation of new computer architectures Circuit characterization Conclusions Outline

84. June 16th, 2000Talk at Intel, Dirk Stroobandt 84 Research question: Is the use of massive optical interconnects at the logic level in general purpose electrical systems meaningful? Research question: Is the use of massive optical interconnects at the logic level in general purpose electrical systems meaningful? Opto- electronic FPGAs Answer depends on whether the properties of optical interconnections are comparable (or better) than those of the electrical ones they replace or complement  Such a situation presents itself in electrical FPGAs

85. June 16th, 2000Talk at Intel, Dirk Stroobandt 85 Area I/O in FPGAs Future multi-FPGA emulators will face the following problems: ASICs will keep growing: the need for multi-FPGA emulators will stay FPGAs will have increasing numbers of CLBs Complex designs have high Rent Exponents  Pin and inter-FPGA interconnect limitations will keep increasing Area I/O provides significant benefits in FPGAs* *J. Depreitere, H. Van Marck, J. Van Campenhout, Microprocessors and Microsystems 21, 1998, pp. 89 -- 97

86. June 16th, 2000Talk at Intel, Dirk Stroobandt 86 (a) gain because wires do not have to be routed all the way to the perimeter Why Area I/O in FPGAs ? Area I/O provides significant benefits in FPGAs* *J. Depreitere, H. Van Marck, J. Van Campenhout, Microprocessors and Microsystems 21, 1998, pp. 89 -- 97 Design size (logic blocks) Area I/O gain over Perimeter I/O (%) (a) gain because wires do not have to be routed all the way to the perimeter (b) gain when pin limitation problems are also considered

87. June 16th, 2000Talk at Intel, Dirk Stroobandt 87 Why 3D FPGAs? Different asymptotic average wire length* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp. 306 -- 315 Two-dimensional Design size (logic blocks) Three-dimensional p =0.4 p =0.6 p =0.8

88. June 16th, 2000Talk at Intel, Dirk Stroobandt 88 Why 3D FPGAs ? Wire length distribution differs significantly* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp. 306 -- 315 Distribution Rent exponent r Average wire length

89. June 16th, 2000Talk at Intel, Dirk Stroobandt 89 Effect of Anisotropy Benefits are lower if anisotropy is higher* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp. 306 -- 315 Number of layers (4096 gates) Average wire length Relative anisotropic cost Average wire length 11 0 4 5 4 3 2 1 51015202528616101214 3 7.5 2.5 6 5 4 3.5 7 6.5 5.5 4.5 Cost = 1 Cost = 16 Cost = 8 Cost = 24

90. June 16th, 2000Talk at Intel, Dirk Stroobandt 90 What Could It Look Like ? A 3-D extension of the electrical on-chip interconnect fabric offers a highly compact and densely interconnected multi-FPGA system should provide an essentially 3-D routing environment, leading to shorter average wire lengths, hence faster systems should provide an increased routability of complex designs Other (hierarchical) interconnect schemes could be envisioned

91. June 16th, 2000Talk at Intel, Dirk Stroobandt 91 Overview of the built system Each FPGA has 128 optical receivers and 128 transmitters System is designed for 80MHz (85 MHz measured) FPGA chip contains about 165,000 transistors About 1/3 of the FPGA chip is used for the optics

92. June 16th, 2000Talk at Intel, Dirk Stroobandt 92 An optical prototype 0.6  m chip standard 145 pin PGA socket 4 x 8 InP detecor arrays 4 x 8 LEDs (VCSELs)

93. June 16th, 2000Talk at Intel, Dirk Stroobandt 93 Conclusion Wire length estimates are becoming more and more important. A priori estimates can provide a lot of information at virtually no cost. Methods are based on Rent’s rule. Important for future research: how can we build a priori estimates into CAD layout tools? More information at http://www.elis.rug.ac.be/~dstr/http://www.elis.rug.ac.be/~dstr/ Check out the International Workshop on System-level Interconnect Prediction (SLIP) at http://vlsicad.cs.ucla.edu/SLIP2000/http://vlsicad.cs.ucla.edu/SLIP2000/