Sungho Kang Yonsei University

Sungho Kang Yonsei University
SCAN Testing Sungho Kang Yonsei University

Outline Introduction Scan Registers Scan Cell Scan Methodology
Scan Length Partial Scan Design Rules Conclusion

Scan Introduction Scan is a test methodology that allows one to control and observe all internal nodes in a synchronous design Application for finite state machines Combinational and sequential elements tested separately Logic Test Two mode operation Normal mode Test mode

Scan Design Introduction

Scan Design Huffman Model of Sequential Circuit Primary Inputs Outputs
Introduction Huffman Model of Sequential Circuit Combinational Circuit F/F Primary Outputs Inputs Clock

Scan Design Normal Mode Primary Primary Inputs Outputs Combinational
Introduction Normal Mode Primary Inputs Primary Outputs Combinational Circuit MUX F/F SCAN OUT SCAN IN MODE

Scan Design Test Mode : Flush Test (shift test of scan path) Primary
Introduction Test Mode : Flush Test (shift test of scan path) Combinational Circuit F/F Primary Outputs Inputs SCAN IN SCAN OUT MODE MUX

Scan Design Test Mode : Scan in of a test vector Primary Inputs
Introduction Test Mode : Scan in of a test vector Combinational Circuit F/F Primary Outputs Inputs SCAN IN SCAN OUT MODE MUX

Scan Design Introduction Test Mode : Apply the test vector to Pi and observe a response at PO Combinational Circuit F/F Primary Outputs Inputs SCANIN SCANOUT MODE MUX

Scan Design Test Mode : Capture response by a clock tick Primary
Introduction Test Mode : Capture response by a clock tick Combinational Circuit F/F Primary Outputs Inputs SCANIN SCANOUT MODE MUX

Scan Design Test Mode : Scan Out of a response Primary Inputs Outputs
Introduction Test Mode : Scan Out of a response Combinational Circuit F/F Primary Outputs Inputs SCAN IN SCAN OUT MODE MUX

Scan Cell Introduction A specialized FF or latch activated only when the design is in scan mode Allows data to be scanned in for control Allows data to be scanned out for observation

Test for Sequential Circuits
Introduction Flush Test Used in two-clock circuits Simultaneously activates both master clock and the scan clock in the scan mode Inputs of 0 and 1 are successively applied at the scan register input Initialize FFs to 0 and shift 1 through FFs Shift Test Used in both two-clock and single-clock circuits This test shift pattern of 0 and 1 through the shift register in the scan mode sequence is shifted through FFs

Scan Design Flow Complete HDL Design using scan design rules
Introduction Complete HDL Design using scan design rules Synthesize logic using the selected ASIC library Convert regular FFs to scan FFs Use test synthesis program Connects the scan data in a serial chain and clocks Generate test patterns automatically

Scan Test Operation Loop
Introduction Put the chip into scan mode Shift data into scan chain through Scan in While scanning in the next pattern through Scan in, scanning out the results through Scan out of the previous pattern Apply the functional clock to latch responses into scan FFs Perform above 2 steps for each test pattern

Scan vs Conventional Test Methods
Introduction Scan Conventional Test Generation Automatic Manual Vector Type Structural Functional Test Coverage Extremely High Low to Medium Vector Set Minimal Large Test Time Short Long Tester Memory Minimal Large

Advantages of Scan Design
Introduction Structured design is possible Can use combinational ATPG Significant reduction of test generation time High fault coverage, typically Ease of fault diagnosis

Disadvantages of Scan Design
Introduction Additional circuitry is added to FF SCAN flip-flop is more expensive Additional chip area Additional circuit pins Performance penalty Increased propagation time Test time increase Due to shift in and shift out Some designs are not easily realizable as scan designs Need to store Patterns Motivation for BIST Inability to test circuits at full speed Motivation for Delay Fault Testing

Scan Registers Simultaneous controllability and observability
Non-simultaneous controllability and observability

Scan Registers Non-simultaneous controllability and observability
Load the scan register with test data by setting T2=1 and clocking CK2 Drive the circuit to a predefined state with T1=0 Load Q2 into latch Q1 Inject signals into the circuit by setting T1=1 Observe OPs by setting T2=0 and clock CK2 once Scan out data by setting T2=1 and clocking CK2

Scan Registers Observability only Combining many observation points

Scan Registers Scan Registers Controllability only

Scan Design Adding controllability and observability to a circuit
Scan Registers Adding controllability and observability to a circuit To inject 0, an AND is used and to inject 1, an OR is used To inject 0 or 1, a MUX is used

Scan Design Controllability/Observability with scan chain
Scan Registers Controllability/Observability with scan chain The normal path from A to B is broken when B1=1 The top row of MUXs is used to inject data into a circuit from scan register The lower row of MUXs is used for monitoring data within the circuit

Full Serial Scan Scan Registers

Isolated Serial Scan Scan register is not in the normal data path
Scan Registers Scan register is not in the normal data path Somewhat ad hoc since CPs and OPs is left up to the designer

Full Isolated Scan High overhead Support real time testing
Scan Registers High overhead Support real time testing A single test can be applied at the operational clock rate of the system Support on-line testing Circuit can be tested while in normal operation

Multiplexed Data Flip-flop
Scan Cell Setting TE = 1 Shifting the test patterns from SI into the flip-flops Setting TE = 0 and after a sufficient time for combinational logic to settle, checking the output values Applying a clock signal CLK Setting TE = 1 and shifting out the flip-flop contents via Q

Two-port Dual-clock Flip-flop
Scan Cell Sometimes it is useful to separate the normal clock from scan clock

Multiplexed Data Shift Register Latch
Scan Cell It is often desirable to insure race-free operation by employing a two-phase non-overlapping clock

Two-port Shift Register Latch
Scan Cell Avoid the delay introduced by the MUX LSSD

Raceless Two-port D Flip-flop
Scan Cell CLK : Control normal operation SK : Select scan data and control scan process

Polarity-hold Addressable Latch
Scan Cell Random access scan Since no shift operation occurs, a single latch per cell is sufficient Latches that are not addressed produce a scan-out value of So = 1 The So output of all latches can be wired-ANDed together to form the scan-out signal Sout

FASCAN Scan Cell No delay in data path Additional MUX in clock path

Scan/Set Use generic isolated scan architecture
Scan Methods Use generic isolated scan architecture Add to the circuit a shift register whose sole purpose is the shifting in and out of test data FFs(test purpose); Ls(system latches converted to 2-port latches) More overhead Possible to gate the latch contents into the test shift register during normal system operation Possible to scan circuit nodes other than latch outputs into the test shift register

Random Access Scan Scan Methods Non-serial Scan

Random Access Scan Scan Methods Treat each one of the latch elements as a bit in memory Each bit in the memory has its own unique address, and it has a port which can load data into the latches so that the contents of the latch can be observed There is only one scan-in and one scan-out Addressing scheme which allows each latch to be uniquely selected, so that it can be either controlled or observed. Normal operation Scan clock is off Only one latch receives the scan clock and that value is loaded into the latch.

LSSD Level Sensitive Scan Design Level sensitive
Scan Methods Level Sensitive Scan Design Level sensitive If the steady state responses to any of the allowed input changes is independent of the transistor and wire delays in the network Polarity-hold hazard-free level-sensitive latch When a clock is enabled, the state of latch is sensitive to the level of the corresponding data input To obtain race-free operation, clocks are non-overlapping Rules for LSSD hazard-free D latches should be used for all system bistables A two-phase latch FSM structure should be used The L1 and L2 latches should be interconnected in a scan path structure

LSSD Scan Methods D: normal data, I: scan data, C: system clock, A: scan clock, B: slave clock Latch a L1 Latch c Latch b L2 A O Scan In B D C I C’ A’ B’

LSSD Double Latch Design
Scan Methods Both L1 and L2 participate in system function

Scan Methods Test Sequence Scan mode: apply AB clock pairs to load SRLs Apply Primary Input stimuli Measure Primary Output response (clocks off) Capture state responses into SRL (eg: pulse C) Scan mode: pulse B clock to copy L1 to L2. Apply AB clock pairs to unload SRLs

Scan Methods Static Testing Capture End Scan in B A X Y C1 L1 L2

LSSD Single Latch Design
Scan Methods Only L1 is used in normal operation Very Expensive Eliminate races

SRL with L2* Latch Additional clock and clocked data port
Scan Methods Additional clock and clocked data port Significant reduction on silicon cost

SRL with L2* Latch D = D1 C = CK1 Q Sin = D2 A = CK2 D C Sin A D1 CK1
Scan Methods D = D1 C = CK1 Q Sin = D2 A = CK2 D C Sin A D1 CK1 D2 CK2 Q L1 L2 B D* C*

Single Latch Design with L2* Latch
Scan Methods

Advantages of LSSD Scan Methods The correct operation of the logic network is independent of AC characteristics such as clock edge rise time and fall time Network is combinational in nature as far as test generation and testing is concerned The elimination of all hazards and races greatly simplifies both test generation and fault simulation

Multiple Test Session Test session Together Mode
Scan Length Test session Configuring scan paths and other logics Testing logic using scan test methodology Together Mode The entire circuit can be tested by 100 test patterns with length of 12 100 X 12 = 1200 clock cycles

Multiple Test Session Separate Mode
Scan Length Separate Mode While C1 is being tested, C2, R3 and R4 are ignored To test C1, 8 X 100 cycles are required To test C2, 8 X 20 cycles are required Total 960 clock cycles

Multiple Test Session Overlapping Mode
Scan Length Overlapping Mode Initially, C1 and C2 can be combined and tested using 20 patterns with length 12 12 X 20 cycles C2 is completely tested and C1 can be tested with remaining 80 patterns with length 8 8 X 80 cycles Total 880 clock cycles

Scan Shift Reduction Target faults for each test vector
Partial Scan Target faults for each test vector If a test vector detects only a few faults, then a few FFs will be required to be controlled or observed for the test vector Arrangement of FFs in the scan chain If FFs which are frequently required to be controlled (observed) are located close to the scan input (output) line, a few scan shift operations are required Order of test vectors Maximize the overlap between successive scan in patterns

Partial Scan Full scan is not always feasible
Retains many advantages of full scan and reduces the cost Exclude certain flip-flops Fault coverage is a function of the number of scan FFs Main researches Flip-flop selection Test length reduction Retiming What do we lose in partial scan? Loss of fault coverage Difficult to automate in synthesis environments

Partial Scan Partial Scan

Partial Scan How to choose scan FFs and non-scan FFs?
Testability Analysis Structural Analysis ATPG Based Analysis Used in conjunction with other schemes

ATPG Based Analysis Partial Scan Begin with a fully scanned circuit and perform empirical evaluation for the removal of scan from each individual FF Select one or more FFs with lowest scan desirability and delete them from the scan point set Repeat the previous step until the phase change conditions are met Run the ATPG system and, if the desired fault coverage is not achieved, select and add scan FFs using the pruned fault set until the desired coverage is achieved or the upperbound on the number of scanned FFs allowed is reached Best results is obtained only when all test patterns for each fault are available

Testability Analysis Perform testability measure
Partial Scan Perform testability measure Based on the results, select FFs Continue the previous steps until upperbound on the number of scanned FFs is selected Simple but low coverage

Testability Analysis SCOAP CC0(Combinational 0 Controllability)
Partial Scan SCOAP CC0(Combinational 0 Controllability) CC1(Combinational 1 Controllability) CO(Combinational Observability) SC0(Sequential 0 Controllability) SC1(Sequential 1 Controllability) SO(Sequential Observability)

Testability Analysis SCOAP d a b D Q DFF e g f c G A B C g Node a b c
Partial Scan SCOAP d a b D Q DFF e g f c G A B C g Node a b c d e f 2 CC0 1 5 CC1 3 CO 4 SC0 SC1 SO

Structural Analysis Circuit Circuit Graph Partially Scanned Circuit 1
Partial Scan Circuit Circuit Graph Partially Scanned Circuit 1 2 3 4 5 6 6 1 2 3 4 5 1 2 3 4 5 6 SCANOUT SCANIN MODE

Structural Analysis Partial Scan Using I-Paths I-mode I-path
A module S with input port X and output port Y has an identity mode (I-mode), denoted by IM( ) if S has a mode of operation in which the data on X is transferred to Y Latches, registers, MUXs, busses, ALUs, etc. I-path An identity transfer path (I-path) exists from output port X of module S1 to input port Y of module S2, denoted as IP( ), if data can be transferred unaltered, but possible delayed Consists of a chain of modules, each of which has an I-mode

Structural Analysis I-mode example MUX IM(MUX: ) ; x = 0 ; t = 10ns
Partial Scan I-mode example MUX IM(MUX: ) ; x = 0 ; t = 10ns IM(MUX: ) ; x = 1 ; t = 10ns ALU IM(ALU: ) ; x1x2 = 00 ; t = 20ns IM(ALU: ) ; x1x2 = 01 ; B=0; Cin=0 Register IM(ALU: ) ; t = 1 clock cycle

Testing Using I-Paths Example Test process of C
Partial Scan Example I-path exists from the output of the block C to input ports of R1, R2 and R3 I-path exists from output ports of R1, R2, R3 and R4 to input port of C Assume that only one register can drive the bus at any one time and a tristate driver is disabled when its control line is high Test process of C Time Controls Operation t1-t Scan into R1 t33 Contents of R1 are loaded onto the bus Data on bus are loaded into R2 t Test pattern is applied to C Response from C is loaded into R3 is loaded onto the bus passes from bus through MUX and is loaded into R1

Testing Using I-Paths Partial Scan Example

Partial Scan Using I-Paths
Design Problems Identifying a subset of registers to be included in the scan path Scheduling the testing of logic blocks Determining efficient ways to activate the control lines when testing a block of logic Determining ways of organizing the scan paths to minimize the time required to test the logic

I-mode Parallel-to-parallel Parallel-to-serial Serial-to-parallel Serial-to-serial Transfer-mode (T-mode) If an onto mapping exists between input port and output port of a module T-path consists of a chain of modules having zero or more I-modes and at least one T-mode I-paths and T-paths are used for transmitting data from a scan register to the input port of a block of logic to be tested Example Array of inverters that maps the input vector X into NOT(X)

Sensitized-mode (S-mode) If a module has a mode of operation such that an error in the data at input port produces an error in the data at output port S-path consists of a chain of modules having zero or more I-modes and at least one S-mode I-paths and S-paths are used for transmitting response to a scan register or primary outputs Example SUM = A+B If B is held at any constant value, an error in A produces an error in SUM

Structural Analysis Partial Scan BALLAST

BALLAST Structured Partial Scan Design
A subset of storage cells is selected and made part of the scan path so that the resulting circuit has a special balanced property Although the resulting circuit is sequential, only combinational ATPG is required and complete coverage if all detectable faults can be achieved Once a test pattern is shifted into the scan path, more than one normal system clock may be achieved before the test result is loaded into the scan path and subsequently shifted out

BALLAST Partial Scan Circuit Model Cloud : Maximal region of connected combinational logic A group of wires forms vacuous cloud if it connects the outputs of one register directly to the inputs of another it represents primary inputs feeding the inputs of a register it represents the outputs of a register that are primary outputs Storage cells are clustered into registers as long as all storage cells share the same clock and control C1, C2, C3 : Nonvacuous clouds A1, A2, A3 : Vacuous clouds

BALLAST Balanced (B-structure) Nonbalanced Example
Partial Scan Balanced (B-structure) For any two clouds v1 and v2, all signal paths between v1 and v2 go through the same number of registers Nonbalanced Example Unequal paths between C1 and C3 Self loop (unequal paths between C and itself)

BALLAST Test procedure
Partial Scan Test procedure Given a B-structure SB, its combinational equivalent CB is the combinational circuit formed from SB by replacing each storage cell in SB by a wire Depth d of SB is the largest number of registers on any path between any two clouds Let T = {t1, … tn} be a complete test set for all detectable stuck at faults in CB Each test pattern ti = {tia, tib } consists of two parts where tia is applied to PIs and tib is applied to PPIs

BALLAST Test procedure of SB Scan in the test pattern tib
Partial Scan Test procedure of SB Scan in the test pattern tib Apply tia to the primary inputs to S While holding tib at the PIs and tib in the scan path, clock the registers in S, d times Place the scan path in its normal mode and clock it once Observe the value on the POs Simultaneously, scan out the results in the scan paths and scan in t(I+1)b

BALLAST Partial Scan To test SB A pattern is shifted into the scan path R3 and R6 and held two clock periods while a test pattern is also applied to the primary inputs A and B After one clock period test results are captured in R1 and R2 After the second clock period test results are captured in R4 and R5 Finally test results are captured in the scan path R3 and R6

BALLAST Partial Scan

BALLAST Partial Scan Any single stuck fault that is detectable in the combinational logic in S is detectable by a test vector Some additional test may be required to detect shorts between the I/O of storage cells To select a minimal number of storage cells to be made part of scan path so that the resulting circuit is a balanced, is NP complete

BALLAST Example Partial Scan

BALLAST Nonbalanced circuits may require sequential ATPG Example
Partial Scan Nonbalanced circuits may require sequential ATPG Example Consider the fault b s-a-1 Fault b s-a-1 is redundant in combinational equivalent of the circuit

Scan Chain Correlation
Partial Scan Unscanned flipflops are corrupted while test vectors are scanned in and while test outputs are scanned out Combinational Circuit M U X MODE SCAN IN SCAN OUT PO’s PI’s n m p q

Partial Scan Solution : Separate clock Combinational Circuit M U X MODE SCAN IN SCAN OUT PO’s PI’s n m p q C1 C2

Partial Scan Solution : Additional logic Combinational Circuit M U X MODE SCAN IN SCAN OUT PO’s PI’s n m p q

Cost Free Scan Partial Scan Use controllability of PIs to establish scan paths through combinational logic Analyzing the circuit to determine all the cost-free scan FFs Selecting the best input vector to establish the maximum number of cost-free scan FFs on the scan chain Example Free scan path is established when X1=0 and X2=1

General Scan Design Rules
Disable asynchronous clears and presets during scan (Required) Most scan types require all asynchronous clears and presets for scan registers to be inactive in the scan mode, so that bits in the scan chain are not cleared as the scan chain is loaded Eliminate internal tristate contention during scan (Required) If internal busses do exist in the design, during scan mode the circuit can be put into a random state that may cause internal bus contention Prevent multiple drivers Disable all drivers with the scan enable signal Add decoding logic to ensure that only one tristate enable is turned on at any time

Disable write signals for RAMs during scan (Required) Important to preserve the content of the RAMs, as well as FIFOs and register files Disable W EN to the RAM with the SCAN EN Disable bidirectional output buffer during scan (Strongly Recommended) During the scan mode, registers along the scan chain will be toggled frequently, thus turning on and off the bidirectional buffers, causing undesirable current spikes Avoid cross coupled NANDs or NORs (Strongly Recommended) Timing simulation(Strongly Recommended) The shifting of data through the scan chain should be thoroughly simulated to verify that there are no timing violations or internal bus contentions due to the scan operation

No combinational Feedback Loops (Strongly Recommended) Use multiple scan chains (Recommended) Test time is related to the length of scan chain The scan enable pin can be shared Multiple chains of different lengths are allowed Scan chain loading using (Recommended) When fanout problem in Q Use lock-up latches (Recommended) Lock-up latches may be necessary between the scan out and scan in of major blocks or when scan chains switches to a separate clock driver to avoid side effects of clock skew Make RAMs reasonably controllable (Recommended) Fully synchronous Design (Recommended) No gated or internally generated clocks

Full Scan Design Rules One clock rule (Required)
All flip-flops must have the same clock, or effectively the same clock When some clocks are not directly controllable from the PIs, the full scan circuit will have to be treated as a sequential circuit

Partial Scan Design Rules
Minimize destructive FFs (Strongly Recommended) Destructive : Flip-flops in scan chain can be reset or clocked during scan Example The mux-scan design uses the same clock for the scan flip-flops as well as the non-scan flip-flops FF3 and FF4 become destructive

Minimize destructive FFs (Strongly Recommended) Use load signal

Minimize destructive FFs (Strongly Recommended) Gating clock

Minimize destructive FFs (Strongly Recommended) Add a scan clock

Partial scan can be selected by submodules or branches of a clock tree (Strongly Recommended) Put an entire branch of the clock tree in the scan chain and multiplex that clock with a scan clock And leave flip-flops driven by another clock tree branch non-scan A higher degree of partial scan is required to achieve desired testability

MUX Scan Design Rules MUX scan chain
Directly controllable clock for scan flip-flops (Required) Internal clocks are not allowed to drive a scan flip-flop unless it is multiplexed with a test clock during scan mode Avoid destructive flip-flops (Highly Recommended)

Dual-Phase Scan Clock Design
Design Rules Two-phased scan clock scan chain

Dual-Phase Scan Clock Design Rule
Design Rules Disable system clock for scan registers during scan mode (Required) Incorrect clock-disabling circuitry Keep internal clocks reasonably controllable (Highly Recommended)

Dual Port Scan Design Design Rules Dual port scan chain

Dual Port Scan Design Rules
Disable system clock for scan registers during scan mode (Required) Illegal scan chain connection The Q output of a scan flip-flop can trigger another scan flip-flop, destroying the scan value at that flip-flop Make sure that the signals driving the normal clocks CK of the scan flip-flops cannot toggle during the scan mode Keep internal clocks reasonably controllable (Highly Recommended)

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