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Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must.

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Presentation on theme: "Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must."— Presentation transcript:

1 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/011 THE WORLD OF LOGIC FAMILIES Source: TI LVXVCXLCX Tiny Logic VCXLCXVCXLCX VHC/ VHCT FST

2 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/012 Source: Insight Onsite WORLDWIDE LOGIC TAM & MARKET SHARE 19981999

3 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/013 PRODUCT LIFE CYCLE Source: TI LS/S SCAN TTL ABT VCX VHC/VHCT FACT FAST/FASTr/ALS HC/HCT ECL IntroductionGrowthMaturitySaturationDeclining CD4000/74C AS TinyLogic LVX/LCX/LVT ALVT FST Source: Fairchild

4 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/014 Bipolar families : Saturation or decline phase 5V CMOS families : maturity or saturation phase except for AHC/AHCT and VHC/VHCT FAMILY RECOMMANDATION Recently discontinued (LTB = 30/04/01) Not recommended for new designs Not recommended for new designs new designs

5 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/015 BiCMOS families : maturity phase for ABT growth phase for LVT (3.3V) and ALVT (2.5V). FAMILY USED RECOMMANDATION new designs 3.3V CMOS families : growth phase. Pay attention with FCT3 New designs

6 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/016 WHO MAKES WHAT ? x x

7 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/017 LOGIC VENDOR PARTNERSHIPS Source: TI

8 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/018 FAMILY PERFORMANCE POSITIONING Source: Texas.Instr.

9 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/019 Source: Fairchild. FAMILY PERFORMANCE POSITIONING

10 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0110 LOW-VOLTAGE LOGIC COMPARISON Source: Fairchild IDT Hitachi, IDT TI FSC, TOSH ON, STm, Pericom FSC, TOSH ON, STm, Pericom ON

11 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0111 LOW-VOLTAGE MARKET COVERAGE Source: TI

12 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0112 LOGIC MIGRATION Source: Fairchild Source: Philips

13 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0113 LOGIC MIGRATION Source: Fairchild

14 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0114 5-Volt Tolerant I/Os ADVANCED-LOGIC FEATURE LIST Output Series Termination Resistors (damping resistor) Live Insertion (Power-up/Power-down 3-State, I OFF) Bus Hold LVC, LVT, ALVT, LCX 5 V TTL bus 5 V bus ABT, ALVT, LVC, LVT ABT, ALVC, ALVT, LVC, LVT, LCX ABT, ALVC, ALVT, LVC, LVT, LCX, VCX

15 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0115 Small package options: Less board space needed Optimized PCB layout: Simplified routing Reduced EMI noise: Better routing possibilities Enhancing ASIC functionality: Quick fixes WCSP - smaller package: Enhanced thermal and electrical performance Benefits LITTLE LOGIC (SINGLE & DUAL GATE) Source: TI

16 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0116 TinyLogic TM HS and HST families drop-in replacements for High-Speed (TC7Sxx) UHS is the fastest available single gate logic All 5-lead functions available in either SOT-23 or SC70 packaging Six lead latches, flip/flops and dual buffers in unique six lead SC70 pkg. Tiny ’00 Quad-gate ’00 HS VHC-like CMOS inputs 5V designs 2mA Drive <25ns max at 5v HST VHCT-like TTL inputs 5V designs 2mA Drive <30ns max at 5v UHS LCX-like CMOS inputs 3V designs (1.65 - 5.5V Vcc) 24mA Drive <5.2ns max at 5v 5v over-voltage tolerant I/O FS FST-like 3V designs (1.65 - 5.5V Vcc) <6 ns enable and disable Low Ron < 7 Ohms High Bandwidth >250 MHz Source: Fairchild

17 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0117 † Symbol or red indicates C i = 30 pF LITTLE LOGIC FEATURES Source: TI

18 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0118 FAIRCHILD’S LOW VOLTAGE LOGIC ROADMAP 74LVXxxx 74LCXxxx74VCXxxx Next Gen 74LVTxxx74ALVTxxx 74HCxxx Vcc : 2-6.0V Tpd : 23nS Ioh/Iol : 6mA Vcc : 2-3.6V Tpd : 7.0nS Ioh/Iol : 4mA Vcc : 2-3.6V Tpd : 4.5nS Ioh/Iol : 24mA Vcc : 0.8-1.5V Tpd : 4nS Ioh/Iol : 2-4mA Vcc : 1.8-3.6V Tpd : 2.5nS Ioh/Iol : 24mA Vcc : 2.7-3.6V Tpd : 3.5nS Ioh/Iol : -32/64mA Vcc : 1.8-3.6V Tpd : 2.5nS Ioh/Iol : -32/64mA Current Drive (Ioh/Iol) 0 mA 64 mA Supply Voltage (Vcc) 7.0 V1.0 V Source: Fairchild

19 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0119 SOT23-5 package outline 2.9 mm 2.84 mm SC70 pkg outline 2.0 mm 2.1 mm Pitch Length WidthArea Height SOT23-5 (M5).95 2.9 2.8 8.1 1.1 SC70-5 (P5).65 2.0 2.1 4.2 1.0 LITTLE LOGIC PACKAGES

20 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0120 LOGIC PACKAGING LIFE CYCLE Source: Fairchild

21 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0121 PACKAGING OPTIONS Source: TI

22 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0122 SELECTING A LOGIC FAMILY Source: TI

23 Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V5.0.0 09/10/0123 LOW VOLTAGE DECISION TREE

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