1. Tom Schulte Low Cost Product Marketing 5/9/2014
MAX 10 FPGAs - Overview
Tom Schulte
Low Cost Product Marketing
5/9/2014
This section is intended to show how the MAX 10 family fits into Altera’s portfolio, a high level look at the MAX 10 family including features & benefits, high level architecture, benefits vs. existing solutions, family plan, package plan, ordering code, schedules, and Early Access Programs.
There is more high level content organized by architectural section (pages ). Use page 21 with embedded bookmarks to jump to the appropriate section and at the end of the subject section, it will return you back to page 21.

2. Innovation Leader Across the Board
PLDs
Lowest Cost, Lowest Power
FPGAs
Cost/Power Balance
SoC & Transceivers
FPGAs
Mid-range FPGAs SoC & Transceivers
FPGAs
Optimized for High Bandwidth
PowerSoCs
High-efficiency Power Management
Resources
Before we go into Altera’s Next Generation LOW COST PROGRAMMABLE DEVICES, let’s pause for a moment and consider the value that Altera brings as an Innovation leader across the board. We provide customers with the largest range of device offerings in the FPGA industry
MAX brand CPLDs
A wide range of FPGAs:
(low-cost) Cyclone FPGAs
(mid-range) Arria FPGAs
(high-performance) Stratix FPGAs
FPGA configuration devices
Enpirion power regulator modules
FPGA industry’s best design tools and IP
Quartus II software
Qsys System Integration tool with System Console
DSP Builder
OpenCL
ARM & Altera’s Nios II 32-bit processor (16 bit version, planned), memory controllers, VIP Suite, etc.
We also want to mention superior product lifecycle management
Typical 15 years+ lifecycle (2x longer than our peers)
Periodic review of product lifecycles to minimize customer pain from obsoleting parts that are still in use
So, when customers partner with Altera, they are getting a width and breadth of products that no other Programmable supplier can offer.
Embedded Soft and Hard Processors
Design
Software
Development
Kits
Intellectual Property (IP)
Industrial
Computing
Enterprise

3. Low Cost Families – Altera Continues Focus & Investment
More performance,
features, or density
Cyclone V
SoC
Next
Generation
FPGA Products
Cyclone V
Cyclone IV
Cyclone III
Cyclone II
Cyclone®
MAX 10
Delivering
Next Generation Products
Looking back the past 10 years, Altera has consistently invested in the Low Cost PLD market segment.
End applications & customers using Low Cost Products remains an Altera Corp. focus.
Since the FPGA market is growing ~ 2x the rate of the CPLD growth, we’ve introduced more Cyclone-class FPGAs over this period of time.
The CPLD market is still important to Altera’s strategy & growth.
I think we have “demonstrated” our commitment to the Low Cost PLD product segment by introducing more low-cost families than any other PLD supplier.
The new MAX 10 FPGAs architecture will have features and densities of both the MAX CPLD and Cyclone FPGA product segments.
MAX 10 will complement but not replace existing MAX II, MAX V, Cyclone IV, and Cyclone V families... In some cases, the new family will offer more features, at lower costs.
Altera also continues to collect customer feedback for Altera’s next generation low-cost architectures.
CPLD Products
MAX V
MAX® II
2000
2013
Future
In Design
Product Planning 3 3 3

4. MAX 10 FPGAs: Revolutionizing Non-Volatile Integration
FPGA Capabilities
Up to 50,000 Logic Elements
Analog Block with ADC
Internal SRAM
PLLs
DSP Blocks
External Memory Interface (e.g. DDR3)
Dual Image Configuration
Nios II Embedded Processor
LVDS, PCI, and 30+ other I/O Standards
Design Security
Sleep Mode
Non-volatile Features
Instant-On
User Flash Memory
Voltage Regulator
Internal Oscillator
MAX 10 is a full featured, general purpose programmable logic family that combines a large number of FPGA features listed here along with all the easy to use features normally associated with CPLDs.

5. MAX 10 FPGAs Simplify FPGA Systems
Traditional FPGA
MAX 10 FPGAs
Vsupply
Vsupply
LDO
LDO
LDO
3.3V
1.2V
2.5V
3.3V
Dual Image
Configuration Device
Traditional FPGA
(Up to 50k LE)
3.3V I/O
Dual Image
Configuration Memory
MAX 10 FPGA
(Up to 50k LE)
3.3V I/O
Shown on the left is a typical FPGA design along with external components frequently used next to an FPGA.
On the right is the MAX 10 implementation, reducing a 6 component solution into 2 components (both available from Altera) and getting into user mode in a few milliseconds (vs. FPGA implementations typically in the 100’s of milliseconds).
Analog
Analog
ADC
Analog Block
Standard
Configuration Time
Instant-On
Configuration

6. MAX 10 FPGAs Increase Capabilities of CPLD Systems
External Memory
Interface
CPLD
3.3V
I/O
Analog
MAX 10 FPGA
User Flash
(Nios code)
Analog
Block
3.3V I/O
DSP
Single Image
Single
Image
Dual Image
CPLD
MAX 10 FPGAs
Logic Elements
240 – 8,000
2,000 – 50,000
Instant-On Images
Single
Dual
DSP No
Yes
DDR3 SDRAM
Analog Block w/ADC
Embedded Processor
Nios II
Shown on the left is a typical CPLD design with limited capabilities. On the right is the MAX 10 implementation, providing options to significantly increase the functionality of typical electronic systems…even the option to add “smart” capability with 32-bit embedded processing which could augment or replace microcontrollers.

7. MAX 10 vs. Prior Family – Higher Single Chip Integration
Feature
MAX V CPLDs
MAX 10 FPGAs
Process Technology
180 nm
55 nm
User Logic (max.)
2,000 LE’s
50,000 LE’s
On-chip Configuration
Single Image
Dual Image, AES
User I/O
271
Up to 500
User Flash Memory
8 Kb
Up to 512 Kb
On-chip hard IP blocks -
Embedded RAM, DSP, ADC, PLL
Remote System Upgrade No
Yes
Here is a quick feature comparison with MAX V CPLDs. You can see that MAX 10 FPGAs add a lot of NEW features which customers can take advantage of to lower total system cost and achieve higher reliability.
Using the latest fab process technology from TSMC, 55nm embedded flash + SRAM, Altera is able to fit many more features on a single programmable chip.
More user logic, more on-chip memory, more, more, more, as compared to prior MAX CPLDs
And, just to be clear, while both products are branded “MAX”, the MAX 10 device is a non-volatile FPGA…more than a CPLD.
Lowering System Cost & Increasing Reliability

8. Main Architecture Modules
MAX 10 FPGA - Floorplan
DSP Blocks
Main Architecture Modules
Logic array
On-chip RAM & FLASH
DSP blocks
Up to two analog blocks
Up to eight I/O banks
Up to four PLL’s
Oscillator & Clocks
Soft IP functionality
Nios® II 32-bit processor, Ethernet MAC, PCIe MAC, Video IP Suite, etc.
RAM Blocks
Analog Blocks
Config.
Flash
User Flash
Control Block
Here’s a look at the floorplan of a typical MAX 10 FPGA device.
You’ll see that logic is organized into the familiar columnar structure with Logic Array Blocks, RAM blocks, and DSP blocks organized vertically up and down the die. It’s got up to 8 I/O banks around the periphery of the die – with multiple banks per side offering more choices for different I/O support per device.
The I/O can interface to a variety of different voltage levels and I/O standards.
The larger density device members (10M16 – 10M50) support the main-stream external memory interfaces: DDR3, DDR2 and LPDDR2. Interfacing to legacy external memory, such as Single Data Rate SDRAM or SRAM, are available on every product.
You can see the analog block (or blocks) in the top left of the die. I’ll describe that in more detail in a few moments.
Plus there’s the Configuration Flash Memory and User Flash Memory also in the top left hand side of the die.
Internal configuration memory Internal configuration memory has the following customer benefits: faster startup time, less board space, and a smaller bill of materials…compared to devices that require external configuration. Another customer benefit of internal configuration storage, increased security because there are no exposed programming interfaces and therefore no way to intercept a configuration bit stream coming into the FPGA because, well, there isn’t one.
And, just for clarification, the on-chip FLASH is NOR type memory which is much more reliable than NAND type memory.
Logic Array Blocks
External Memory Interfaces
PLL’S

9. MAX 10 FPGA – Family Plan Device LEs Block Memory (Kb) User Flash 1
Mults
PLLs
Internal
Config.
ADC 4, TSD
External
RAM
I/F
10M02
2,000
108 96 16
1, 2
Single -
Yes 2
10M04
4,000
189
128 19
Dual
1, 1
10M08
8,000
378
256 24
10M16
16,000
549 45
1, 4
Yes 3
10M25
25,000
756 61
2, 1
10M40
40,000
1,260
512
125
10M50
50,000
1,638
144
Here is the family table showing the resources of the family…ranging from 2,000 user logic elements (LE’s)…an ample amount of logic resources for the majority of control plane, simple glue logic functions…all the way up to 50,000 LE’s.
There is an ample amount of on-chip RAM and FLASH memory…along with 18x18 multipliers that can be used for massively parallel DSP processing for things like filtering or image processing.
High performance, low-jitter PLLs and global clock networks provide lots of on-chip clocking resources.
The # of PLL’s available is dependent on the package option…lower pin-count packages only have 1 PLL, F256 or higher pin-count packages have the maximum number of PLLs available.
Not shown here but the # of global clocks available = 10 or 20 (10M02-08 has 10 clocks, 10M16-50 has 20 clocks).
All of the devices are self-configured and store the device image(s) within secure, integrated FLASH (this is NOT die stack…i.e. Xilinx Spartan-3AN).
Another 1st for Altera…the inclusion of up to 2 on-chip analog blocks (ADC + temperature sensing diode).
For the larger densities devices, we’ve added some on-chip optimization to simplify creating I/O interfaces to external double data rate SDRAM memories.
Note 1 - Under certain conditions, additional on-chip FLASH memory will be available to the user…potentially another 500 Kbits up to 5 Mbits. This would be very useful for Nios CODE storage.
Notes:
Additional User Flash may be available, depending on configuration options.
SDR SDRAM or SRAM only.
SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2.
ADC blocks available on die but may not be available in low pin count packages.
Preliminary and subject to change without notice.

10. MAX 10 FPGA - Feature Set Options
C: Compact
F: Flash
A: Analog
Single Image
Yes
Dual Image
w/Remote System Upgrade -
Analog Features Block
“C” “F” “A”
There are three feature set options in the family you can choose from…denoted with the letters C, F, and A.
With a “C” class device, you will get a single boot image is stored within the device.
With an “F” class device, you will get single-chip dual configuration image support (an industry 1st) and remote system upgrade capability.
And, with an “A” class device, you will get all of the above plus the analog block.
You can consider the C-version to be the “Compact” version, which will be the least expensive option for customers. The “F” and “A” variants will give customers access to additional FUNCTIONS and thus will be priced higher than the “C” variant.
Three Feature Set Variants To Order From

11. Package Plan & Available I/O (Dual Power Supply: 1.2V/2.5V)
Product
Line
36-WLCSP
3x3mm2
0.4mm Pitch
81-WLCSP
4x4mm2
256-FBGA
17x17mm2
1.0mm Pitch
324-UBGA
15x15mm2
0.8mm Pitch
484-FBGA
23x23mm2
672-FBGA
27x27mm2
10M02 “D”
C (27) -
C (160)
10M04 “D”
C/F/A (178)
C/F/A (246)
10M08 “D”
C/F (56)
C/F/A (250)
10M16 “D”
C/F/A (320)
10M25 “D”
C/F/A (360)
C/F/A (380)
10M40 “D”
C/F/A (500)
10M50 “D”
Note: Selected items = Pro-active automotive p/n rollout.
Other product line/package combinations available upon request & sufficient ROI.
Preliminary and subject to change without notice
C: Compact
F: Flash
A: Analog
Besides the three feature set options, there are two voltage regulator options…with or without the on-chip voltage regulator permanently enabled.
Let’s look at the Dual Power Supply PACKAGE options first (NOTE – these devices do NOT have the internal regulator enabled).
The device density will range from one to 50 thousand logic elements with C, F, and A variants scattered across the package options as shown.
Package sizes range from extremely small to larger BGA packages with ball pitch ranging from 0.4mm - 1.0mm ball.
The number in the parenthesis equals the # of user I/O available, ranging from 27 to 500.
Also, I wish to point out that even though we don’t ADVERTISE this on Altera.com, we do support selling bare die to select customers (INTERNAL NOTE: Customer opportunity must meet minimum order qty’s, ROI, legal addendum, and agree with technical restrictions).
Bare
Die
WLCSP
xBGA
U = 0.8mm ball spacing
F = 1.0mm ball spacing
Wide Variety of Sizes & Available I/O

12. Package Plan & Available I/O (Single Power Supply: 3.3V)
Product
Line
144-EQFP
16x16 mm2
0.4 mm Pitch
153-MBGA
8x8mm2
0.5mm(1)
169-UBGA
11x11mm2
0.8mm
10M02 “S”
C (101)
C (112)
C (130)
10M04 “S”
C/F/A (101)
C/F/A (112)
C/F/A (130)
10M08 “S”
10M16 “S” -
10M25 “S”
10M40 “S”
10M50 “S”
Notes:
1 – “Easy PCB” utilizes 0.8mm PCB design rules
2 - Items in blue = Pro-active automotive p/n’s.
Others available upon request & sufficient ROI.
Preliminary and subject to change without notice
C: Compact
F: Flash
A: Analog
Here are the package options for the Single-Supply devices (NOTE – these have the internal regulator enabled):
The device density will also range from one to 50 thousand logic elements.
I/O counts range from 103 to 130 for the single power supply parts.
Looking at the M153 package, we’ve devised an innovative way to provide customers with a small physical size package with good amount of I/O.
<< click on the hyperlink to jump to a back-up slide illustrating this innovative new idea >>
Bare
Die
xBGA
M = 0.5mm ball spacing
U = 0.8mm ball spacing
EQFP
Single Supply Option for
Simplicity & Convenience

13. MAX 10 FPGA Ordering Information
Optional
Suffix
Family
10M: MAX 10 FPGA ES
G = RoHS 6
P = Leaded
ßß = Special processing
10M 16 x x u484 i 7 x ßß
Product
Line
Speed
6, 7, 8
6 = fastest,
8 = slowest
02: 2K LE’s
04: 4K LE’s
08: 8K LE’s
16: 16K LE’s
25: 25K LE’s
40: 40K LE’s
50: 50K LE’s
Power
Supply
Feature
Option
Package Type
& Ball Count
Grade /
Temperature
Here is the part number format for the family. Please check with your Altera sales person for valid p/n’s since every permutation of the combination these features is not available. (NOTE – you can also get valid p/n’s from Quartus II s/w).
S: Single Voltage
D: Dual Voltage
C: Compact features
F: Flash features
A: Analog features
V: Wafer level chip-scale
E: EQFP
M: MBGA
U: UBGA
F: FBGA
36, 81
144
153
169, 324
256, 484, 672
C: Commercial (TJ = 0°C to +85°C)
I: Industrial (TJ = -40°C to +100°C)
A: Automotive (TJ = -40°C to +125°C)

14. MAX 10 FPGA I/O Standard Support
Variant
Toggle Rate 1 (MHz)
Max Strength
Load
Application
Single-Ended
LVTTL/LVCMOS 3.3V
2 mA
10 pF
General purpose
LVTTL/LVCMOS 3.0V
250
16 mA
LVTTL/LVCMOS 2.5V
LVTTL/LVCMOS 1.8V
12 mA
LVTTL/LVCMOS 1.5V
8 mA
LVTTL/LVCMOS 1.2V
200
PCI -
Schmitt Trigger (RX only)
External Memory Interfaces
(& Voltage Referenced I/O)
SSTL2 Class I
12mA/50 W
7 pF
DDR1
SSTL2 Class II
16 mA/25 W
SSTL18 Class I
300
DDR2
SSTL18 Class II
SSTL15 Class I
DDR3
SSTL15 Class II
SSTL15
34 W
SSTL135
DDR3L
HSUL12
LPDDR2
HSTL18 Class I
DDR2+/QDR2+/RLDRAM2
HSTL18 Class II
HSTL15 Class I
DDR2+/QDR2/QDR2+/RLDRAM2
HSTL15 Class II
HSTL12 Cass I
12 mA/50 W
HSTL12 Class II
14 mA/25 W
LVDS
Dedicated LVDS (RX/TX) 3
830/800 Mbps
6 pF 2
Dedicated Mini-LVDS (TX) 3
380 Mbps
Dedicated RSDS (TX) 3
340 Mbps
Dedicated PPDS (TX) 3
420 Mbps
External Resistor LVDS (TX)
600 Mbps
External Resistor Mini-LVDS (TX)
External Resistor RSDS (1R) (TX)
170 Mbps
External Resistor RSDS (3R) (TX)
342 Mbps
External Resistor PPDS (TX)
LVPECL (RX only)
830 Mbps
BLVDS (RX/TX)
830/475 Mbps
Programmable logic is frequently used to translate between different components which have different I/O voltage levels or I/O standards. As you can see, MAX 10 supports a large number of I/O options.
(INTERNAL NOTE: The majority of die/pkg combinations are NOT available in the fastest speed grade. Please check the specific p/n’s to ensure it is available to quote and available in Quartus. For any questions on a p/n, please contact the nearest Low-Cost Product Marketing person).
Notes:
Toggle rate (maximum) assumes max. drive strength, fastest slew rate setting for the specified load, and fastest speed grade (–c6).
Measured on a single pin, not pair.
Only available on the bottom I/O banks (Bank3, Bank4).

15. 3 Early Access Programs for MAX 10 FPGA
2013
2014
Jul.
Aug.
Sept.
Oct.
Nov.
Dec.
Jan.
Feb.
Mar.
Apr.
May
Jun.
#1 - EIP
Rev.
13.1
Rev.
14.0
Rev.
14.1
#2 - ESP
Device Handbook
MAX 10 FPGA
#3 - EDP
There are three early access programs offered before the family is LAUNCHED. The goal is to get information to customers as soon as possible before the family is publically available.
EIP
Benefits to customers = Get information early to help decide if these devices can meet your technical requirements. The sign-up process:
Customer to “opt-in” to receive s.
Sales to fill out form (download from MOLSON) & to factory
ESP
If you’re convinced MAX 10 devices can meet your technical requirements and your schedule requires early s/w and device deliveries in 2H 2014, speak with your local Altera sales person to see if you can be admitted into the S/W BETA program. We limit the number of customers because all the customer documentation isn’t yet available, so we have to support customers individually (we have a limited amount of resources).
Selection criteria
Customers must be willing to take BETA s/w, GUI’s, IP, limited documentation, etc.
Or Altera partners working on key projects (IP, kits, or virtual ASSP)
Or large $ opportunities (INTERNAL NOTE: Greater than $1M and must be Altera “friendly”)
(INTERNAL NOTE: Approvals needed:
Product Marketing & BU mgr. prioritization & approvals required
For Xilinx or Lattice “friendly” customers, BU director or Sales RVP approval needed )
EDP
The goal is to align our first shipments of devices to customers who have proto schedules that can’t wait for Altera to complete all of the functional check-out prior to shipment.
Early Information Program
Unlimited # of customers
Monthly bulletins
Advanced Info. Brief
Preliminary handbook
Other “specials”
Early Software Program
Limited # of customers
Hidden S/W in v13.1 (10M08 only)
Production S/W in v14.0 (all devices)
Compilation & early timing
EPE
Early Device Program
Limited # of customers
ES and/or EAP device shipments
10M04, 08, 40, and 50 ES p/n’s
Early .POF / .SOF support

16. MAX 10 FPGAs revolutionize non-volatile integration
MAX 10 FPGAs Summary
MAX 10 FPGAs revolutionize non-volatile integration
Single-chip, non-volatile solution with the smallest footprint
Only dual-persona single-ship, non-volatile solution
Integrated ADC and other system-cost saving hard IP
Up to 95% dynamic power savings via sleep mode
Ideal for both datapath and control plane applications
MAX 10 FPGA
Devices
MAX 10 FPGAs are highly integrated devices offering many popular FPGA features along with other value added functions like analog to digital conversion, non-volatile memory capability, all packaged into a single, easy to design re-programmable device.
MAX 10 FPGA devices can reduce the system cost if the DESIGN can take advantage of any of the on-chip hard IP blocks (RAM, FLASH, ADC, PLL, DSP, ETC.) allowing those functions implemented in other components to be absorbed into a single, programmable component.
We didn’t talk about the details earlier but the new sleep mode can dramatically reduce the device’s dynamic power.
The investment to get started and design for MAX 10 FPGA is minimal…all the s/w support is included in Altera’s Quartus II web edition, download it for free, and get your license file on-line. On-line training classes are also available.
( INTERNAL NOTE: To handle any MAX 10 FPGA pricing questions, please download and reference the March 2014 (or later) MSVP price guidelines).
FPGA
Non-Volatile

17. What’s Next?
1H 2014 Early Information Program
2H 2014 Devices & Dev Kits Shipping
If you are interested in continuing to receive MAX 10 related information, would you sign up for the Early Information Program (EIP)?
We need you to agree to “opt-in”.
(INTERNAL NOTES:
Must have mutual NDA legal agreement in place to participate in EIP program.
Sales person should now take the time for “uncovering” to learn more about the customers interest, any project details, specific technical requirements, any things they didn’t like, etc. After this “uncovering” conversation, you can then move on to answering some technical questions starting on page 21.)
Would you sign-up for monthly updates on MAX 10 FPGAs (with valid NDA)?

18. Back-Up Information

19. MAX 10 FPGA M153 Package – “Easy PCB” Footprint
Intentionally created gaps in ball grid array to allow space for PCB traces and/or through-hole via’s.
Goal: “Easy” PCB board design
Use 0.8mm pitch design rules instead of 0.5mm rules.
2 layer signal breakout (SMD on both component and PCB)
3 mil line/space
16 mil PTH
Shared P/G PTH
Avoiding use of blind or buried via’s.
Minimize the number of PCB layers needed to route to all device pins.
8mm
Altera will create and update existing Application Note 114 – Design Guidelines for BGA packages to include a PCB layout recommendation for this new M153 package.
0.5mm
8mm
Note: Altera recommended PCB layout (preliminary) in 4Q 2013 
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