1. 8089 I/O PROCESSOR (INDEPENDENT PROCESSOR)

2. Instead of having each interface communicate with the CPU , a computer may have one or more external processor and assign them the task of communicating directly with all I/O devices

3. 8089 IO processor The characteristic features of 8089 are as follows:
Very high speed DMA capability—I/O to memory, memory to I/O, memory to memory and I/O to I/O.
1 MB address capability.
8086, 88 compatible.
Supports local mode and remote mode I/O processing.
Allows mixed interface of 8-and 16-bit peripherals
Memory based communications with CPU.
Supports two I/O channels
On each of the two channels of 8089, data can be transferred at a maximum rate of 1.25 MB/second for 5MHz clock frequency

4. 8089 Architecture

5. Channels:
CPU sends out a channel attention signal along with SEL signal which selects the channel SEL=0 channel 1,SEL=1 channel 2
The activities of the two channels are controlled by CCU.
occupy two consecutive IO port addresses
Contains same set of registers(Pointer register and other registers)
Each pointer registers has a tag bit indicates weather the pointer represents a memory space address(tag=0) or IO address(tag=1).Task pointer stores the address of the next instruction to be executed. It also contains tag bit

6. DRQ and EXT
DRQ is used to initiate DMA transfer while EXT for termination of the same.
A high on DRQ1 tells 8089 that a peripheral is ready to receive/transfer data via channel 1.
A high on EXT causes termination of current DMA operation if the channel is so programmed by the channel control register. This signal must be held active (= 1) until termination is complete
SINTR
stands for signal interrupt. It is an output pin from 8089
be connected through an 8259 interrupt controller.
A high on this pin alerts the CPU that either the task program has been completed or else an error condition has occurred
LOCK
when active, this output pin prevents other processors from accessing the system buses

7. Control register format
Control signals
Control register format
Function control (D15 and D14)
Translation mode D13
Synchronous control D12 &D11
Source and Destination control D10
Lock control D9
Chaining control D8
Single transfer mode D7
Termination control (D6-D0)

8. A few of the application areas of 8089 are
File and buffer management in hard disk/floppy disk control.
Provides for soft error recovery routines and scan control.
CRT control such as cursor control and auto scrolling made simple with 8089.
Keyboard control, communication control, etc.

9. Communication between CPU and IOP

11. Communication process
Communication between the CPU and IOP takes place through messages in shared memory and consists of five linked memory message blocks (ABCDE or ABCD’E’) with ABC representing the initialization process
The process of initialization begins with 8089 IOP receiving a reset at its RESET input
On the falling edge of CA, the SEL input is sensed. SEL = 0/1 represent Master (Remote)/Slave (Local) configuration. (during any other CA, the SEL line indicates selection of CH1/CH2 depending on SEL = 0/1 respectively

13. 5 bytes of information from system memory starting from FFFF6 H is read into 8089.
The first byte determines the width of the system bus.
The subsequent bytes are then read to get the system configuration pointer (SCP) which gives the locations of the system configuration block (SCB)
The BUSY flag in CB is removed, signaling the end of the initialization process.
It should be noted that the address of SCP—the system configuration pointer resides in ROM and is the only one to have fixed address in the hierarchy. Since SCB resides in RAM, hence it can be changed to accommodate additional IOPs, to be inducted into the system

14. Channel command word formatP B
ICF CF
P-Priority Bit
B:1-Bus load limit ,0-No busload limit
ICF: Interrupt Control Field
00-Ignore
01-Remove interrupt request
10-Enable interrupts
11-Disable interrupts
CF: command field
000-Update PSW
001-Start channel program located in IO space
010-Reserved
011-Start channel program located in IO space
100-Reserved
101-Resume suspended channel program
110-suspend channel program
111-Halt channel program

15. Once initialization is over, any subsequent hardware CA input to IOP accesses the control block (CB) bytes for a particular channel -the channel (1 or 2) which gets selected depends on the SEL status
All except the task block must be located in memory accessible to the 8089 and the host processor