1. Digital Electronics and Logic Design
Md. Ebtidaul KArim

2. Counters
A sequential circuit that goes through a prescribed sequence of states upon the application of the input pulse is called counter.
A counter that follows the binary sequence is called binary counter.
An n bit binary counter consists of n flip flops and can count in binary from 0 to 2 𝑛 −1.
Here the state transition occurs during the clock pulse; flip-flops remain in the present state if no pulse occurs.
Here we don not show CP explicitly as input variable.
So state diagram of counter does not have to show input output value along directed lines.
Here the only input to the circuit is clock pulse and outputs are directly specified by the present states of the flip-flops.

3. Counters
Next state of the counter depends entirely on the present state and the state transition occurs every time the pulse occurs.
Fig: State Diagram of 3-bit binary counter

4. Counters
Binary counters are most efficiently constructed with T flip flops. Why ??
Because any state transition occurs when T is equal to 1, as T stands for toggle flip flop.
Three flip flops in 3 bit binary counter are given designation 𝐴 0 , 𝐴 1 and 𝐴 2 .
The excitation table for 3- bit binary counter 3 present state ,3 next state and 3 flip flop input column.
It has 8 rows for representing 8 states.

5. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 2

6. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

7. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

8. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

9. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

10. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

11. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

12. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

13. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

14. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

15. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

16. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

17. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

18. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

19. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

20. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

21. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

22. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

23. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

24. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

25. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

26. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21

27. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

28. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

29. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

30. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21 1

31. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21
Excitation table for 3 bit counter

32. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21
𝐴 1 𝐴 0 00 01 11 10 1
𝐴 2
𝑇 𝐴 2 = 𝐴 0 𝐴 1

33. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21
𝐴 1 𝐴 0 00 01 11 10 1
𝐴 2
𝑇 𝐴 1 = 𝐴 0

34. Counters Present State Next State Flip Flop Inputs 𝐴 2 𝐴 1 𝐴 0 T 𝐴 21
𝐴 1 𝐴 0 00 01 11 10 1
𝐴 2
𝑇 𝐴 0 =1

35. Counters From the above three equation, 𝑇 𝐴 2 = 𝐴 0 𝐴 1 𝑇 𝐴 1 = 𝐴 0
𝑇 𝐴 2 = 𝐴 0 𝐴 1
𝑇 𝐴 1 = 𝐴 0
𝑇 𝐴 0 =1
We will get the following circuit diagram

36. Counters H.W: Design a 3 bit binary counter with JK Flip flops.
Design a counter that count decimal numbers 0,1,3,5,7,0 in binary form with JK flip flop.
Design a counter that count decimal numbers 0,1,3,5,7,0 in binary form with SR flip flop
Design a counter that count decimal numbers 0,1,3,5,7,0 in binary form with T flip flop.

37. Counters There are mainly two types of counter. Such as:
Ripple Counter
Synchronous Counter
In a ripple counter flip flop output transition serves as source for triggering other flip flops. Here CP inputs of all flip flops except the first one are triggered not by the incoming pulse, but by transition that occurs in other flip flops.
In synchronous counter input pulses are applied to all CP inputs of all flip flops.

38. Counters Binary Ripple Counter
A 4-bit binary ripple counter can count from 0000 to It consists of 4 flip flops.
Here output of each flip flop is connected to the CP input of the next higher order flip flop.
Here all the J and K inputs are equal to 1.
Small circle in the input of the CP indicates that flip flop triggers at the negative transition of the pulse, that is when the output to which it is connected goes from 1 to 0.
Every time 𝐴 1 goes from 1 to 0, it compliments 𝐴 2 and so on up to 𝐴 4 .
The flip flops change one at a time in rapid succession and signal propagates through a counter in a ripple fashion. It is also known as asynchronous counter.

39. Counters CP 𝐴 1 𝐴 2 𝐴 3 𝐴 4 Here positive transition
Binary Ripple Counter CP
𝐴 1
𝐴 2
𝐴 3
𝐴 4
Here positive transition
Negative transition
Here t is the number of total clock pulse. t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Output of the flip flop changes only at the negative transition of the output of previous flip flop

40. Counters Binary Ripple Counter:
𝐴 4
𝐴 3
𝐴 2
𝐴 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Binary Ripple Counter:
From the timing sequence obtained in the previous slide for 17 complete clock pulses, we get the following table:

41. Counters Binary Down Counter:
A binary counter with a reverse count is called binary down counter.
In a countdown counter, the binary count is decremented by 1 with every input count pulse.
The count of a four‐bit countdown counter starts from binary 15 and continues to binary counts 14, 13, 12, , 0 and then back to 15.
The diagram of a binary countdown counter looks the same as the binary ripple counter provided that all flip‐flops trigger on the positive edge of the clock.

42. Counters
Binary Down Counter: Here t is the number of total clock pulse. t CP
𝐴 1
𝐴 2
𝐴 3
𝐴 4
Here positive transition
Negative transition
Output of the flip flop changes only at the negative transition of the output of previous flip flop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

43. Counters Binary Down Counter:
If negative‐edge‐triggered flip‐flops are used, then the C input of each flip‐flop must be connected to the complemented output of the previous flip‐flop.
Then, when the true output goes from 0 to 1, the complement will go from 1 to 0 and complement the next flip‐flop as required.

44. Counters Binary Ripple Counter:
It is a decimal counter follows a sequence of 10 states and returns to 0 after the count of 9.
Such a counter must have at least four flip‐flops to represent each decimal digit, since a decimal digit is represented by a binary code with at least four bits.
If BCD is used, the sequence of states is as shown in the state diagram

45. Counters BCD Ripple Counter:
The logic diagram of a BCD ripple counter using JK flip‐flops.
The four outputs are designated by the letter symbol Q, with a numeric subscript equal to the binary weight of the corresponding bit in the BCD code.
Output of Q1 is applied to the C inputs of both Q2 and Q8 and the output of Q2 is applied to the C input of Q4.
The J and K inputs are connected either to a permanent 1 signal or to outputs of other flip‐flops.

46. Counters BCD Ripple Counter:
At first we need to remember the JK characteristics table.
Here we see output is complimented when both J and K is 1.

47. Counters BCD Ripple Counter:1 1 1 1
𝑄 1 is complimented on the negative edge of the count pulse.
𝑄 2 is complimented if 𝑄 8 =0 and 𝑄 1 goes from 1 to 0. 𝑄 2 is cleared if 𝑄 8 =1 and 𝑄 1 goes from 0 to 1.
𝑄 4 is complimented when 𝑄 2 goes from 1 to 0.
Negative Transition 1 1 1 1 1 1 1 1
𝑄 8 is complimented when 𝑄 4 𝑄 2 =1 and 𝑄 1 goes from 1 to 0. 𝑄 8 is cleared if either 𝑄 4 or 𝑄 2 is 0 and 𝑄 1 goes from 1 to 0.
Negative Transition 1 1 1

48. Counters BCD Ripple Counter: CP 𝑄 1 𝑄 2 𝑄 4 𝑄 8 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1

49. Counters Three Decade Decimal BCD Counter: Decimal Value
A 4-bit BCD ripple counter can count from 0 to 9 in decimal.
After counting 9 it again starts from 0.
So at the beginning it will count 0000 or decimal 0

50. Counters Three Decade Decimal BCD Counter: Decimal Value 1× 10 1 +9=191 1 1 9
It will count up to decimal 9.
After counting 9, it will again start count from 0000 or decimal 0 . 1
As 𝑄 8 changes from 1 to 0 and as 𝑄 8 acts as count pulse of second BCD counter, 𝑄 1 of 2nd BCD changes from 0 to 1.

51. Counters Three Decade Decimal BCD Counter: Decimal Value 9× 10 1 +9=99
1× =10
1× =19
2× =20 1 1 1 1 1 1 1 1
1st BCD will again count up to 1001 or decimal 9.
After counting 9, it will again start count from 0000 or decimal 0 . 1
As 𝑄 8 changes from 1 to 0 and as 𝑄 8 acts as count pulse of second BCD counter, 2nd BCD counts 0010 or decimal 2
In this way we can count up to 99

52. Counters Three Decade Decimal BCD Counter: Decimal Value 9× 10 1 +9=991 1 1 1
After Counting 1001 or decimal 9, 1st BCD will count 0000 or decimal 0.
As 𝑄 8 changes from 1 to 0 and as 𝑄 8 acts as count pulse of second BCD counter, value of 2nd counter is incremented by 1 and becomes 0000. 1 1

53. Counters Three Decade Decimal BCD Counter: Decimal Value
1× =100 1
As 𝑄 8 of 2nd counter changes from 1 to 0 and as 𝑄 8 acts as count pulse of 3rd BCD counter, 𝑄 1 of 3rd BCD changes from 0 to 1.
In this way we can count up to decimal 999 with three-decade decimal BCD counter.

54. Counters Synchronous Counter: 4-Bit Binary Counter with JK Flip Flop:
Here we can count from 0000 to 1111 with 4 JK flip flops.
We know that in synchronous counter all the flip flops are triggered by same clock pulse. So here we don’t need to construct timing sequence to show the operation of the counter.
We can simply design the counter from the state table, considering the excitation table of the JK flip flop.
Previously we have designed a 3-bit binary counter with T flip flop. But here as we are designing 4-bit counter we have 4 present state and next state column. Again as we are designing with JK flip flop and as JK flip flop has two inputs we need two columns for each present state column.

55. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X

56. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

57. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

58. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X 1 X

59. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

60. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

61. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X 1 X

62. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X 1

63. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

64. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

65. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

66. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X 1 X

67. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

68. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X 1 X

69. Counters Synchronous Counter: Present State Next State
XFlip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X 1

70. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X 1

71. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

72. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

73. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X X

74. Counters Synchronous Counter: Present State Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X 1 X
Similarly by following the above steps we can get the table up to present state 1111

75. Counters Synchronous Counter: State Table of 4 bit Binary up counter
Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
Synchronous Counter:
State Table of 4 bit Binary up counter

76. Counters 𝐴 2 𝐴 1 00 01 11 10 1 X 𝐴 4 𝐴 3 𝐽 𝐴 1 =1 Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 1 X
𝐴 4 𝐴 3
𝐽 𝐴 1 =1

77. Counters 𝐴 2 𝐴 1 00 01 11 10 X 1 𝐴 4 𝐴 3 𝑘 𝐴 1 =1 Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 X 1
𝐴 4 𝐴 3
𝑘 𝐴 1 =1

78. Counters 𝐴 2 𝐴 1 00 01 11 10 1 X 𝐴 4 𝐴 3 𝐽 𝐴 2 = 𝐴 1 .1 Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 1 X
𝐴 4 𝐴 3
𝐽 𝐴 2 = 𝐴 1 .1

79. Counters 𝐴 2 𝐴 1 00 01 11 10 X 1 𝐴 4 𝐴 3 𝑘 𝐴 2 = 𝐴 1 .1 Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 X 1
𝐴 4 𝐴 3
𝑘 𝐴 2 = 𝐴 1 .1

80. Counters 𝐴 2 𝐴 1 00 01 11 10 1 X 𝐴 4 𝐴 3 𝐽 𝐴 3 = 𝐴 1 𝐴 2 Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 1 X
𝐴 4 𝐴 3
𝐽 𝐴 3 = 𝐴 1 𝐴 2

81. Counters 𝐴 2 𝐴 1 00 01 11 10 X 1 𝐴 4 𝐴 3 𝐾 𝐴 3 = 𝐴 1 𝐴 2 Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 X 1
𝐴 4 𝐴 3
𝐾 𝐴 3 = 𝐴 1 𝐴 2

82. Counters
Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 1 X
𝐴 4 𝐴 3
𝐽 𝐴 4 = 𝐴 1 𝐴 2 𝐴 3

83. Counters
Present State
Next State
Flip Flop Inputs
𝐴 4
𝐴 3
𝐴 2
𝐴 1
J 𝐴 4
K 𝐴 4
J 𝐴 3
K 𝐴 3
J 𝐴 2
K 𝐴 2
J 𝐴 1
K 𝐴 1 1 X
𝐴 2 𝐴 1 00 01 11 10 X 1
𝐴 4 𝐴 3
𝐾 𝐴 4 = 𝐴 1 𝐴 2 𝐴 3

84. Counters Synchronous Binary Counter Flip Flop Input Equations are:
𝐽 𝐴 1 =1
𝐾 𝐴 1 =1
𝐽 𝐴 2 = 𝐴 1 .1
𝐾 𝐴 2 = 𝐴 1 .1
𝐽 𝐴 3 = 𝐴 1 𝐴 2
𝐾 𝐴 3 = 𝐴 1 𝐴 2
𝐽 𝐴 4 = 𝐴 1 𝐴 2 𝐴 3
𝐾 𝐴 4 = 𝐴 1 𝐴 2 𝐴 3

85. Counters Binary Up-Down Counter1 1
Binary Up-Down Counter
When the up input is 1, the circuit counts up, since the T inputs receive their signals from the values of the previous normal outputs of the flip‐flops.

86. Counters Binary Up-Down Counter
Binary Up-Down Counter 1 1 1 1
When the up input is 1, the circuit counts up, since the T inputs receive their signals from the values of the previous normal outputs of the flip‐flops.
When the down input is 1 and the up input is 0, the circuit counts down, since the complemented outputs of the previous flip‐flops are applied to the T inputs.

87. Counters Binary Up-Down Counter
Binary Up-Down Counter 1
When the up input is 1, the circuit counts up, since the T inputs receive their signals from the values of the previous normal outputs of the flip‐flops.
When the down input is 1 and the up input is 0, the circuit counts down, since the complemented outputs of the previous flip‐flops are applied to the T inputs.
When the up and down inputs are both 0, the circuit does not change state and remains in the same count.

88. Counters As showing the whole counter procedure is lengthy.
We take a random number, say 1011.
Now 1 1
Binary Up-Down Counter 1 1
When the up input is 1, the circuit counts up, since the T inputs receive their signals from the values of the previous normal outputs of the flip‐flops.
When the down input is 1 and the up input is 0, the circuit counts down, since the complemented outputs of the previous flip‐flops are applied to the T inputs.
When the up and down inputs are both 0, the circuit does not change state and remains in the same count.
When the up and down inputs are both 1, the circuit counts up. This set of conditions ensures that only one operation is performed at any given time.

89. Counters Binary Up-Down Counter1 1
Binary Up-Down Counter 1 1 1
As showing the whole counter procedure is lengthy.
We take a random number, say 1101.
Now if we want to perform up operation, we set Up=1 and Down=0 1 1 1 1
As input of 𝑇𝐴 1 flip flop is 1, output toggles
Although output of 𝑇𝐴 1 changes from 1 to 0, red color AND gate takes the previous value of 𝑇𝐴 1 , which is 1, as there is a delay in flip flop.
As both the inputs of red color AND gate is 1, output is 1 1 1

90. Counters Binary Up-Down Counter1 1
Binary Up-Down Counter 1 1 1
As input of 𝑇𝐴 2 flip flop is 1, output toggles. 1 1
Although output of 𝑇𝐴 2 changes from 0 to 1, blue color AND gate takes the previous value of 𝑇𝐴 2 , which is 0, as there is a delay in flip flop.
As the input of the of one blue color AND gate is 0. output is 0 1 1 1 1
As input of 𝑇𝐴 3 flip flop is 0, output do not toggles.
As the input of the of one yellow color AND gate is 0. output is 0. 1

91. Counters Binary Up-Down Counter1 1
Binary Up-Down Counter 1 1 1
As input of 𝑇𝐴 4 flip flop is 0, output do not toggles.
So the counter counts 1110 and its initial value was 1101.
So after setting up=1, initial value is incremented by 1. 1 1 1 1 1 1 1

92. Counters Binary Up-Down Counter Again we take the number, say 1101.
Binary Up-Down Counter 1 1 1 1 1 1 1 1
Again we take the number, say 1101.
Now if we want to perform down operation, we set Up=0 and Down=1 1
As input of 𝑇𝐴 1 flip flop is 1, output toggles
Although output of 𝑇𝐴 1 changes from 1 to 0, red color AND gate takes the previous value of 𝑇𝐴 1 , which is 1, as there is a delay in flip flop.
As one of the inputs of red color AND gate is 0, output is 0. 1 1

93. Counters Binary Up-Down Counter
Binary Up-Down Counter 1 1 1 1 1 1 1 1
Again compliment of 𝑇𝐴 1 changes from 0 to 1, yellow color AND gate takes the previous value of 𝑇𝐴 1 , which is 0, as there is a delay in flip flop. 1 1
As one of the inputs of yellow color AND gate is 0, output is 0.
As input of 𝑇𝐴 2 flip flop is 0, output do not toggles. 1
As input of 𝑇𝐴 3 flip flop is 0, output do not toggles.
As input of 𝑇𝐴 4 flip flop is 0, output do not toggles.
So the counter counts 1100 and its initial value was 1101.
So after setting down=1, initial value is decremented by 1. 1

94. Counters Synchronous BCD Counter:
A BCD counter counts in binary‐coded decimal from 0000 to 1001 and back to 0000.
Because of the return to 0 after a count of 9, a BCD counter does not have a regular pattern, unlike a straight binary count.
Here we design a 4-bit BCD counter with 4 T-flip flop.
In this counter there is also an output y, which is equal to 1 when the present state is In this way, y can enable the count of the next‐higher significant decade while the same pulse switches the present decade from 1001 to 0000.

95. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1

96. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

97. Counter State Table for BCD: 1
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1
Now look at the excitation table of T- flip flop.
Q(t)
Q(t+1) T 1

98. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

99. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

100. Counter State Table for BCD: 1 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1

101. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

102. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

103. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1

104. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1

105. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

106. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

107. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

108. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1

109. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

110. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1

111. Counter State Table for BCD: 1 Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1

112. Counter State Table for BCD: 1
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1 1
Similarly if we put the flip flop input values according to excitation table of T-flip flop we will get the following table

113. Counter State Table for BCD: Present State Next State Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1

114. Counter State Table for BCD: Here, Y= 𝑄 8 𝑄 1 𝑄 2 𝑄 1 00 01 11 10
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1
𝑄 2 𝑄 1 00 01 11 10 X 1
𝑄 8 𝑄 4
Here, Y= 𝑄 8 𝑄 1

115. Counter State Table for BCD: Here, T 𝑄 8 = 𝑄 8 𝑄 1 + 𝑄 4 𝑄 2 𝑄 1
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1
𝑄 2 𝑄 1 00 01 11 10 X 1 1
𝑄 8 𝑄 4
Here, T 𝑄 8 = 𝑄 8 𝑄 1 + 𝑄 4 𝑄 2 𝑄 1

116. Counter State Table for BCD: Here, T 𝑄 4 = 𝑄 2 𝑄 1 𝑄 2 𝑄 1 00 01 11 10
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1
𝑄 2 𝑄 1 00 01 11 10 X 1 1
𝑄 8 𝑄 4
Here, T 𝑄 4 = 𝑄 2 𝑄 1

117. Counter State Table for BCD: Here, T 𝑄 2 = 𝑄 8 ⋰ 𝑄 1 𝑄 2 𝑄 1 00 01 11
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1
𝑄 2 𝑄 1 00 01 11 10 X 1 1 1 1
𝑄 8 𝑄 4
Here, T 𝑄 2 = 𝑄 8 ⋰ 𝑄 1

118. Counter State Table for BCD: Here, T 𝑄 1 =1 𝑄 2 𝑄 1 00 01 11 10
Present State
Next State
Output
Flip Flop inputs
𝑄 8
𝑄 4
𝑄 2
𝑄 1 Y
T 𝑄 8
T 𝑄 4
T 𝑄 2
T 𝑄 1 1
𝑄 2 𝑄 1 00 01 11 10 1 X
𝑄 8 𝑄 4
Here, T 𝑄 1 =1

119. Counter Here we get the following equation: T 𝑄 1 =1 T 𝑄 2 = 𝑄 8 ⋰ 𝑄 1
Y= 𝑄 8 𝑄 1
Now draw the counter on the basis of the above equation. H.W.

120. Counter Binary Counter with Parallel Load:
Counters employed in digital systems quite often require a parallel‐load capability for transferring an initial binary number into the counter prior to the count operation.
The four control inputs: Clear, Clock, Load and Count determines the next state.
When the clear input is zero it causes counter to be cleared regardless of the clock, load and count input.
This relationship is indicated in the table by the X entries, which symbolize don’t‐care conditions for the other inputs.
Clear
Clock
Load
Count
Function X
Clear to 0

121. Counter X X
Binary counter becomes zero, regardless of clock, load and count X

122. Counter
The Clear input must be in the 1 state for all other operations. 1
As count and load are 0, we obtain:
As a result output of all the AND gates in left side are 0
As a result output of all the AND gates in right side are 0. 1
Here indicates positive edge

123. Counter
Now, as inputs of all OR gate in right side is 0, J and K of all the flip flops are zero. 1
As a result the values of 𝐴 1 , 𝐴 2 , 𝐴 3 and 𝐴 4 are 0.
As a result carry output is also 0 1

124. Counter
So we can say, with the Load and Count inputs both at 0, clear at 1, the outputs do not change, even when clock pulses are applied.
So function table for counter becomes:
Now if we set load input to 1, while clear is 1 and clock pulse applied we will see the following result
Clear
Clock
Load
Count
Function X
Clear to 0 1
No change

125. Counter X
As a result output connected to count will be 0, regardless of count input. 1 1 1 1 1 1 1 1
Now let us take the values of 𝐼 4 , 𝐼 3 , 𝐼 2 and 𝐼 1 are respectively 0011
As inputs of 2nd OR gate from the top are 0, output, that is K of first counter is 0
As J and K of top most flip flop is 1 and 0 respectively so 𝐴 1 becomes 1. 1

126. Counter X
As output of AND gate connected to count is 0, output of all the AND gates at right will be zero. 1 1 1 1 1 1 1 1 1 1 1 1
As J and K of the 2nd flip flop from the top is 1 and 0 respectively so 𝐴 2 becomes 1 1 1 1
Now as 𝐼 3 is 0, we get:
As J and K of the 3rd flip flop from the top is 0 and 1 respectively so 𝐴 3 becomes 0 1

127. Counter Now as 𝐼 4 is 0, we get:X
Now as 𝐼 4 is 0, we get: 1 1 1 1 1 1 1
As J and K of the 4th flip flop from the top is 0 and 1 respectively so 𝐴 4 becomes 0 1 1 1 1 1
As 𝐴 3 and 𝐴 4 are 0, carry output, which is the AND output of counter output will be zero. 1 1 1
Here we see that inputs are loaded to the counter register when load is 1, clear 1, clock positive, regardless of the value of count. 1 1 1 1

128. Counter So the function table for counter becomes: Clear Clock LoadX
Clear to 0 1
Load Inputs
No change

129. Counter Let the value stored in the register be 00111
When load is 0 and count is 1, we get the : X 1
As output of 2nd inverter is 0, output of all the AND gates at left side will be 0 X X
So whatever be the value in input, it will not pass to the counter. X
Now since both the input is 0, output of the AND gate connected to count will be 1 1

130. Counter As output of AND gate connected to count is 1, we get:1 1 1 X
As J and K of top most flip flop is 1 and 1 so value of 𝐴 1 toggles from 1 to 0 1 1 X 1 1 1 1
But as the previous value of 𝐴 1 was 1, and count AND output 1, output of AND gate at top right will be 1 1 X X
As J and K of 2nd top most flip flop is 1 and 1 so value of 𝐴 2 toggles from 1 to 0 1

131. Counter 1
Now as previous value of 𝐴 1 , 𝐴 2 and AND gate output connected to count is 1, output of 2nd top-right AND gate will be 1. 1 1 1 1 1 X 1 1
As J and K of the 3rd top most flip flop is 1 and 1 so value of 𝐴 2 toggles from 0 to 1 X 1 1 1 1 1 1 X 1 1 1
But as the previous value of 𝐴 3 was 0, output of AND gate at bottom right will be 0 X
As J and K of bottom flip flop is 0 and 0 so value of 𝐴 4 will remain 0. 1

132. Count next binary Value
Counter
So the counter output will be 0100.
Initial value of counter was So counter value is incremented by 1. So we can say circuit counts next binary state when clear is 1, clock positive, load 0 and count 1.
So function table of counter becomes:
Clear
Clock
Load
Count
Function X
Clear to 0 1
Load Inputs
Count next binary Value
No change

133. Timing Signal
The control unit that supervises the operations in a digital system would normally consists of timing signals that determine the time sequence in which the operations are executed.
Timing sequence in the control unit can be easily generated by means of counter of shift register.
What is shift register???
A register( group of binary cells suitable for holding binary information) capable of shifting its binary information either to the right or to the left is called shift register.
Each clock pulse shift the content of the register one bit position to the right

134. Timing Signal
A ring counter is a circular shift register with only one flip flop being set at any particular time.
Let the initial value is 1000, which produces the variable 𝑇 0 1
In this way 4 unique timing signal are generated 1 CP
𝑇 0
𝑇 1
𝑇 2
𝑇 3 1 1 1

135. Timing Signal
Similarly the timing signal can be generated by continuously enabling a 2 bit counter that goes through 4 distinct states.
The decoder decodes the four states of the counter and generates the required sequence of timing signal.

136. Timing Signal 1 1 1
𝑇 0
𝑇 1
𝑇 2
𝑇 3 1 1 1 1 1

137. Timing Signal
In this way we can generate 2 𝑛 timing signals either by a shift register with 2 𝑛 flip flops or by an n bit counter with an n to 2 𝑛 line decoder.
It is also possible to generate the timing signal with a combination of the shift register and decoder.
Here the number of flip flop is less than ring counter and decoder requires only two input gates.
Johnson counter is such a combination.

138. Johnson Counter
A k ‐bit ring counter circulates a single bit among the flip‐flops to provide k distinguishable states.
The number of states can be doubled if the shift register is connected as a switch‐tail ring counter.
A switch‐tail ring counter is a circular shift register with the complemented output of the last flip‐flop connected to the input of the first flip‐flop.

139. Johnson Counter
The register shifts its contents once to the right with every clock pulse, and at the same time, the complemented value of the E flip‐flop is transferred into the A flip‐flop.
Let initial value be Now when clock pulse is applied we get:
Sequence Number
Flip Flop Outputs A B C E 1 1

140. Johnson Counter
Now complimented value of E is the input of flip flop A.
This input is loaded to output(since it is D flip flop where output is same as input) at positive transition of next clock pulse, which is sequence number 2.
Sequence Number
Flip Flop Outputs A B C E 1 2 1 1 1

141. Johnson Counter
At the next positive transition of the clock complimented output of E, which is 1 is loaded to A flip flop and output of A flip flop, which is also 1 is loaded to B flip flop.
Sequence Number
Flip Flop Outputs A B C E 1 2 3 1 1 1 1

142. Johnson Counter
At the next positive transition of the clock complimented output of E, which is 1 is loaded to A flip flop and output of A and B flip flop, which are also 1 is loaded to B and C flip flop respectively.
Sequence Number
Flip Flop Outputs A B C E 1 2 3 4 1 1 1 1 1

143. Johnson Counter
At the next positive transition of the clock complimented output of E, which is 1 is loaded to A flip flop and output of A, B and C flip flop, which are also 1 is loaded to B, C and E flip flop respectively.
Sequence Number
Flip Flop Outputs A B C E 1 2 3 4 5 1 1 1 1 1 1

144. Johnson Counter
At the next positive transition of the clock complimented output of E, which is 0 is loaded to A flip flop and output of A, B and C flip flop, which are also 1 is loaded to B, C and E flip flop respectively.
Sequence Number
Flip Flop Outputs A B C E 1 2 3 4 5 6 1 1 1 1

145. Johnson Counter
At the next positive transition of the clock complimented output of E, which is 0 is loaded to A flip flop and output of A, B and C flip flop, which are 0, 1 and 1 are loaded to B, C and E flip flop respectively.
Sequence Number
Flip Flop Outputs A B C E 1 2 3 4 5 6 7 1 1 1

146. Johnson Counter
At the next positive transition of the clock complimented output of E, which is 0 is loaded to A flip flop and output of A, B and C flip flop, which are 0, 0 and 1 are loaded to B, C and E flip flop respectively.
Sequence Number
Flip Flop Outputs A B C E 1 2 3 4 5 6 7 8 1 1
At the next clock pulse we will get flip flop output of 0000, which is the value of the output at sequence number 1. So there is 8 distinct sequence number

147. Johnson Counter
Johnson counter is a k‐ bit switch‐tail ring counter with 2 k decoding gates to provide outputs for 2 k timing signals.
The eight AND gates listed in the table below, when connected to the circuit, will complete the construction of the Johnson counter.
Since each gate is enabled during one particular state sequence, the outputs of the gates generate eight timing signals in succession.
The decoding of a k‐ bit switch‐tail ring counter to obtain 2 k timing signals follows a regular pattern.

148. AND Gate Required For Output
Johnson Counter
Sequence Number
Flip Flop Outputs
AND Gate Required For Output A B C E 1 2 3 4 5 6 7 8
The all‐0’s state is decoded by taking the complement of the two extreme flip‐flop outputs.
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
The all‐1’s state is decoded by taking the normal outputs of the two extreme flip‐flops.
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
All other states are decoded from an adjacent 1, 0 or 0, 1 pattern in the sequence.
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

149. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸 1

150. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

151. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

152. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

153. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

154. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

155. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

156. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

157. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸 1

158. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

159. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸 1

160. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

161. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

162. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

163. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

164. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

165. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸

166. Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸
Similarly we can fill up the rest of the table

167. 0Generated Timing signal though AND gate output
Johnson Counter
Sequence Number 1 2 3 4 5 6 7 8
Flip Flop Outputs A B C E
0Generated Timing signal though AND gate output
𝐴 ⋰ 𝐸 ⋰
𝐴 𝐵 ⋰
𝐵 𝐶 ⋰
𝐶 𝐸 ⋰ AE
𝐴 ⋰ 𝐵
𝐵 ⋰ 𝐶
𝐶 ⋰ 𝐸
So with a K-bit switch tail counter we can generate 2k timing signal.

168. Thank You