1. THE INTERCONNECT

2. The Wire
schematics
physical

3. Interconnect Impact on Chip

4. Wire Models
Capacitance-only
All-inclusive model

5. Impact of Interconnect Parasitics
reduce reliability
affect performance and power consumption
Classes of parasitics
Capacitive
Resistive
Inductive

6. Nature of Interconnect
Global Interconnect S
Global
= S
Die S
Local
= S
Technology
Source: Intel

7. Nature of Interconnect

8. INTERCONNECT

9. Capacitance of Wire Interconnect

10. Capacitance: The Parallel Plate Model

11. Permittivity

12. Fringing Capacitance

13. Fringing versus Parallel Plate

14. Inter-wire Capacitance (1)

15. Interwire Capacitance (2)

16. Impact of Interwire Capacitance

17. Wiring Capacitances (0.25 mm CMOS)

18. Inter-Wiring Capacitances (0.25 mm CMOS)

19. INTERCONNECT

20. Wire Resistance r L
R =
H W
Sheet Resistance L R H R R 1 2 W

21. Interconnect Resistance

22. Dealing with Resistance
Selective Technology Scaling
Use Better Interconnect Materials
reduce average wire-length
e.g. copper, silicides
More Interconnect Layers

23. Polycide Gate MOSFET Silicides: WSi TiSi , PtSi and TaSi
PolySilicon
SiO 2 n + n + p
Silicides: WSi 2,
TiSi 2
, PtSi
and TaSi
Conductivity: 8-10 times better than Poly

24. Sheet Resistance

25. Modern Interconnect

26. Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric

27. INTERCONNECT
Dealing with Inductance

28. Wire Inductance L H W

29. INTERCONNECT
Interconnect Modeling

30. Modeling Wires Lumped Capacitance Model Lumped Resistance
Lumped Inductance
Distributed & Lumped RC Model
Transmission Line Model

31. Small Interconnect Resistance assumed
The Lumped Model
Clumoed = L x cwire
Small Interconnect Resistance assumed
50 % t = ln(2)t = 0.69t
90 % t = ln(9)t = 2.2t

32. Lumped Resistance/Inductance
Useful for Supply line Modeling
Parasitic Resistance causes supply voltage drop.
Parasitic Inductance causes bouncing on supply rail.

33. The Lumped RC-Model The Elmore Delay

34. The Ellmore Delay RC Chain

35. Wire Model Assume: Wire modeled by N equal-length segments
For large values of N:

36. The Distributed RC-line
R = L.r
C=L.c
t(Vout) = RC = rcL2
Diffusion Equation

37. Step-response of RC wire as a function of time and space

38. RC-Models

39. Driving an RC-line
Condition for dominant wire

40. Design Rules of Thumb
rc delays should only be considered when tpRC > tpgate of the driving gate
Lcrit >  tpgate/0.38rc
rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line
trise < 0.9 RC
Lcrit >  trise/0.9rc
when not met, the change in the signal is slower than the propagation delay of the wire
For metal interconnect L = 3.2 mm in a 1.0 µm technology

41. Creating RC-Models for SPICE
Only 3% Error

42. The Transmission Line Model

43. Lossless Transmission Line - Parameters
Speed of light vacuum
Relative permeability of
insulator
Relative permittivity of
insulator

44. Wave Propagation Speed

45. Lossless Transmission Line - Model
Characteristic Impedance
50 – 100 

46. Wave Reflection for Different Terminations
Reflection Coefficient

47. Transmission Line Response

48. Transmission Line Response (RL= )

49. Lattice Diagram

50. When to Consider Transmission Line Effects? (1)
Rule of Thumb
For on-chip wires of up to 1 cm tr <150 psec
For board wires of up to 50 cm tr <8 nsec

51. When to Consider Transmission Line Effects? (2)
Otherwise distributed RC Model should be used
Combining two conditions

52. When to Consider Transmission Line Effects Examples (1)
Hard to achieve in
Current technologies

53. When to Consider Transmission Line Effects Examples (2)

54. Loss Less Transmission Line Model for SPICE
Approach One: Transmission Delay TD
Approach Two: A Frequency F together with
Normalized Electrical Length of the Transmission Line NL
NL = F . TD