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FPGA’s 9/22/08
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Basic types of FPGA’s One time programmable
Reprogrammable (non-volatile) Retains program when powered down SRAM-based reprogramable Must be reprogrammed each time powered up Xilinx Spartan 3E
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Spartan-3E Architecture Fundamental Elements
Configurable Logic Blocks (CLBs) Consists of RAM based look up table to implement logic and storage elements that can be used as flip-flops or latches. Input Output Blocks (IOBs) Controls the flow of data between IO pins and internal logic. Supports many different signal standards. (Tri-state, bidirectional, LVTTL, etc. Block RAM (BRAM) – 18 Kbit dual ported RAM 18 bit Multiplier Blocks Digital Clock Manager (DCM)
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• Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications • Multi-voltage, multi-standard SelectIO™ interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
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CLB’s
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Spartan 3E IO Blocks (IOB’s)
IOB’s control flow of data between IO pins and the internal logic. Each IOB supports bidirectional data flow, 3-state operation, and numerious different signal standards. (We will typically use LVTTL). See data sheet.
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I/O block
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I/O block continued
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CLB’s – four slices per CLB
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Spartan 3 Configurable Logic Blocks (CLB’s)
CLBs contain Ram based lookup tables to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logic functions as well as store data.
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Top slice of CLB
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