Presentation is loading. Please wait.

Presentation is loading. Please wait.

Charles Weems and Tim Richards University of Massachusetts Amherst

Published byRidwan Tanuwidjaja Modified over 4 years ago

Similar presentations

Presentation on theme: "Charles Weems and Tim Richards University of Massachusetts Amherst"— Presentation transcript:

1 Charles Weems and Tim Richards University of Massachusetts Amherst
CoGenT: Automatic Co-Generation of Compilers & Simulators for Dynamically Compiled Languages Eliot Moss, presenter Charles Weems and Tim Richards University of Massachusetts Amherst BARC 1/30/03

2 Plan of the talk Motivation Generating back-end components
Generating simulator components Machine description languages Our approach

3 Motivation Performance of modern languages Explore hardware features
Java as well as C, Fortran Dynamic compilation, GC, exceptions ... Explore hardware features Estimate performance (time, energy, …) Goal: good estimates of performance via simulation

4 We need a simulator that ...
Supports new hardware feature(s) Has accurate performance measures Handles language implementation Dynamic code generation User-mode signal handlers Memory mapping, including SEGV

5 AND we need a compiler that ...
Produces code for the (new) target Does so dynamically Optimizes competently for the target Hard if features very novel Not so bad for ordinary back-end tasks Instruction selection Register allocation Instruction scheduling

6 Need to automate all of this ...
Hard to get simulators right Especially if you want them fast Time-consuming to develop them Can say the same about compilers Point: Generate both, automatically, from machine descriptions

7 Generating back-ends Prototype framework: Jikes RVM
“Baseline” and optimizing compilers Instruction selection Register allocation Instruction scheduling Requires simple timing simulator

8 Generating back-end components
BURS, Cattell, & Instruction selection Jikes RVM (compiler) Framework Machine descriptions Java bytecode semantics baseline compiler Machine Description ISA syntax & semantics Java bytecode semantics baseline compiler object layout LIR semantics BURS rules Machine Description ISA syntax & semantics LIR semantics BURS rules Machine Description ISA syntax & semantics register allocation info Instruction scheduler info simple instruction timing simulator

9 Generating back-end components
Register allocation & Instruction scheduling Jikes RVM (compiler) Framework Machine descriptions baseline compiler object layout Machine Description ISA syntax & semantics object layout Java bytecode semantics BURS rules LIR semantics register allocation info Machine Description ISA syntax & semantics register allocation info Instruction scheduler info simple instruction timing simulator Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics Instruction scheduler info simple instruction timing simulator

10 Generating simulator components
Functional simulation Instruction semantics Memory contents/function OS calls Timing simulation Pipelines (instruction, FU timing) Caches, memories, busses, … Mix and match ISAs, pipelines, etc.

11 Additional simulator components
Instrumentation and tracing Easy to adjust Debugging and control

12 Generating simulator components
Functional simulation semantics support components Machine descriptions Simulator Framework Memory, addressing, program loading, environment, etc Machine Description ISA syntax & semantics functional simulator functional simulator Java bytecode semantics LIR semantics Cache models, TLB models, memory bus, etc timing simulator Machine Description ISA syntax & semantics debugging support Target pipeline description timing support components

13 Generating simulator components
Timing simulation semantics support components Machine descriptions Simulator Framework Memory, addressing, program loading, environment, etc functional simulator Java bytecode semantics LIR semantics Cache models, TLB models, memory bus, etc Machine Description ISA syntax & semantics Target pipeline description timing simulator timing simulator Machine Description ISA syntax & semantics debugging support Target pipeline description timing support components

14 Machine description languages and their applications
SLED [Ramsey and Fernández] λ-RTL [Ramsey and Davidson] Facile [Schnarr] MLRISC [George and Leung] Annotated pipeline graph [Milner] CCL [Bailey and Davidson] We will assemble the best from these

15 The CoGenT prototype Milner Schnarr Cattell SLED,MLRISC,λ-RTL,etc.
Simulator Framework Machine descriptions Jikes RVM (compiler) Framework BURS rules baseline compiler LIR semantics Machine Description ISA syntax & semantics Java bytecode semantics baseline compiler timing simulator functional Machine Description ISA syntax & semantics functional simulator Support components object layout LIR semantics Machine Description ISA syntax & semantics Java bytecode semantics Target pipeline description Java bytecode semantics BURS rules timing simulator Instruction scheduler info simple instruction timing simulator timing simulator Target pipeline description LIR semantics register allocation info Machine Description ISA syntax & semantics debugging support Instruction scheduler info simple instruction timing simulator Target pipeline description

Download ppt "Charles Weems and Tim Richards University of Massachusetts Amherst"

Similar presentations

Programming Technologies, MIPT, April 7th, 2012 Introduction to Binary Translation Technology Roman Sokolov SMWare

Programming Technologies, MIPT, April 7th, 2012 Introduction to Binary Translation Technology Roman Sokolov SMWare
Program Representations. Representing programs Goals.

Program Representations. Representing programs Goals.
Carnegie Mellon Lessons From Building Spiral The C Of My Dreams Franz Franchetti Carnegie Mellon University Lessons From Building Spiral The C Of My Dreams.

Carnegie Mellon Lessons From Building Spiral The C Of My Dreams Franz Franchetti Carnegie Mellon University Lessons From Building Spiral The C Of My Dreams.
Enabling Efficient On-the-fly Microarchitecture Simulation Thierry Lafage September 2000.

Enabling Efficient On-the-fly Microarchitecture Simulation Thierry Lafage September 2000.
Modern Compiler Internal Representations Silvius Rus 1/23/2002.

Modern Compiler Internal Representations Silvius Rus 1/23/2002.
Representing programs Goals. Representing programs Primary goals –analysis is easy and effective just a few cases to handle directly link related things.

Representing programs Goals. Representing programs Primary goals –analysis is easy and effective just a few cases to handle directly link related things.
Term Project Overview Yong Wang. Introduction Goal –familiarize with the design and implementation of a simple pipelined RISC processor What to do –Build.

Term Project Overview Yong Wang. Introduction Goal –familiarize with the design and implementation of a simple pipelined RISC processor What to do –Build.
Java for High Performance Computing Jordi Garcia Almiñana 14 de Octubre de 1998 de la era post-internet.

Java for High Performance Computing Jordi Garcia Almiñana 14 de Octubre de 1998 de la era post-internet.
February 21, 2008 Center for Hybrid and Embedded Software Systems Mapping A Timed Functional Specification to a Precision.

February 21, 2008 Center for Hybrid and Embedded Software Systems Mapping A Timed Functional Specification to a Precision.
From Cooper & Torczon1 Implications Must recognize legal (and illegal) programs Must generate correct code Must manage storage of all variables (and code)

From Cooper & Torczon1 Implications Must recognize legal (and illegal) programs Must generate correct code Must manage storage of all variables (and code)
Introduction & Overview CS4533 from Cooper & Torczon.

Introduction & Overview CS4533 from Cooper & Torczon.
Ronny Krashinsky Seongmoo Heo Michael Zhang Krste Asanovic MIT Laboratory for Computer Science SyCHOSys Synchronous.

Ronny Krashinsky Seongmoo Heo Michael Zhang Krste Asanovic MIT Laboratory for Computer Science SyCHOSys Synchronous.
CS-2710 Computer Organization Dr. Mark L. Hornick web: faculty-web.msoe.edu/hornick – CS-2710 info syllabus, homework, labs… –

CS-2710 Computer Organization Dr. Mark L. Hornick web: faculty-web.msoe.edu/hornick – CS-2710 info syllabus, homework, labs… –
Overview of the Course Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.

Overview of the Course Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
Instruction Selection II CS 671 February 26, 2008.

Instruction Selection II CS 671 February 26, 2008.
1 A Simple but Realistic Assembly Language for a Course in Computer Organization Eric Larson Moon Ok Kim Seattle University October 25, 2008.

1 A Simple but Realistic Assembly Language for a Course in Computer Organization Eric Larson Moon Ok Kim Seattle University October 25, 2008.
Java Virtual Machine Case Study on the Design of JikesRVM.

Java Virtual Machine Case Study on the Design of JikesRVM.
1 Fast and Efficient Partial Code Reordering Xianglong Huang (UT Austin, Adverplex) Stephen M. Blackburn (Intel) David Grove (IBM) Kathryn McKinley (UT.

1 Fast and Efficient Partial Code Reordering Xianglong Huang (UT Austin, Adverplex) Stephen M. Blackburn (Intel) David Grove (IBM) Kathryn McKinley (UT.
Instrumentation in Software Dynamic Translators for Self-Managed Systems Bruce R. Childers Naveen Kumar, Jonathan Misurda and Mary.

Instrumentation in Software Dynamic Translators for Self-Managed Systems Bruce R. Childers Naveen Kumar, Jonathan Misurda and Mary.
Presentation by Tom Hummel OverSoC: A Framework for the Exploration of RTOS for RSoC Platforms.

Presentation by Tom Hummel OverSoC: A Framework for the Exploration of RTOS for RSoC Platforms.

Similar presentations

Ads by Google