1. ADSP 21065L

2. Ch.Ramesh
Embedded Systems

3. Features of ADSP 21065L
High performance signal computer for communications, audio, automotive instrumentation and industrial applications.
Super HARWARD architecture computer (SHARC) for independent buses for dual data , instructions, and IO fetch on a single cycle.
32 bit fixed point and 40 bit fixed and floating point arithmetic.
544 Kbit on chip SRAM memory and integrated IO peripheral.
66 MIPS, 198 MFLOPS peak, sustained performance.
User configurable 544 Kbits on chip SRAM memory, two external port, DMA channels and eight serial port, DMA channels.
SDRAM controller for glue less interface to low cost external 66MHzs.
64 Mwords external address range.
Ch.Ramesh
Embedded Systems

4. Code compatibility with all 2106x family processors.
Flexible data formats and 40bit extended precision.
32 bit single precision and 40 bit extended precision floating point data formats.
32 bit fixed point data format computation integer and fractional with dual 80 bit accumulator.
Parallel computation
Single cycle multiply and ALU operations in parallel with dual memory read writes with instructon fetch.
Multiply with add and subtract for accelerated FFT butterfly computation.
1024 point complex FFT bench mark 0.274ms.
544 kbits on chip SRAM DMA controller.
Host processor interface Multiprocessing
Serial ports.
Ch.Ramesh
Embedded Systems

5. ADSP 21000 FAMILY CORE ARCHITECTURE
Ch.Ramesh
Embedded Systems

6. Ch.Ramesh
Embedded Systems

7. DATA ADDRESS GENERATOR WITH HARDWARE CIRCULAR BUFFERS
INDEPENDENT PARALLEL COMPUTATION UNITS: the arithmetic logic unit, multiplier, shifter alll perform single cycle instruction.
The three units are arranged in parallel, maximize the computational throughput.
Single multifunction instructions execute parallel ALU and multiplier operations.
DATA REGISTE FILE : the general purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results.
SINGLE CYCLE FETCH OF INSTRUCTIONS AND TWO OPERANDS : in the chip the data memory data and the proram memory transfers both instructions and data .
INSTRUCTION CACHE
DATA ADDRESS GENERATOR WITH HARDWARE CIRCULAR BUFFERS
FLEXIBLE INSTRUCTION SET.
Ch.Ramesh
Embedded Systems

8. Clock – 33MHz SDRAM – 66MHz External RAM – 33MHz Serial ports – 33MHz
Multiprocessing – 33MHz
Host – 33MHz
Ch.Ramesh
Embedded Systems

9. ADSP 21065l FEATURES DUAL PORTED ON-CHIP MEMORY
OFF CHIP MEMORY AND PERIPHERAL INTERFACE.
SDRAM INTERFACE
HOST PROCESSOR INTERFACE
DMA CONTROLLER
SERIAL PORTS
PROGRAMMABLE TIMERS AND GENERAL PURPOSE IO PORTS
PROGRAM BOOTING
MUTIPROCESSING
Ch.Ramesh
Embedded Systems

10. DUAL PORTED ON CHIP MEMORY
It contains 544Kbits of on chip SRAM.
The RAM is organized into two banks.
Bank – Kbits - 2k x 16 9 columns
Bank – Kbits – 2k x 16 8 columns
Dual ported for single cycle – independent access by the core processor.
16k x 32 bits, 34k x 16 and 10k x 48 bits
memory blocks can store combination code and data accesses are more efficient with respect DM And PM
Ch.Ramesh
Embedded Systems

11. OFF CHIP MEMORY AND PERIPHERAL INTERFACE:
64 M words off chip address space
Separate on chip buses for program data and IO are multiplexed at the external port to create an external system bus with a single 24 bit address bus.
Single 32 bit data bus.
SDRAM INTERFACE
HOST PROCESSOR INTERFACE
HBR and HBG READY
8, 16, 32 bit
Ch.Ramesh
Embedded Systems

12. It has two synchronous serial ports.
DMA COONTROLLER
The DMA controller operates independently and is invisible to processor. The processor allow DMA operations to occur simultaneously while it is executing its program instructions.
DMA transfers can occur between int, ext, ext peripherals or host processor and serial ports.
10 channel DMA is available with 8 via serial ports and two via processor external port.
DMAR|+, DMAG|,
SERIAL PORTS :
It has two synchronous serial ports.
They can operate 1 x clock frequency an d providing the data rate of 33Mbits / sec.
Serial port data can be automatically transferred to and from on chip memory through DMA.
The word lengths that can be transferred is from 3 bits to 32 bits.
They can be used for inter processor communication.
Ch.Ramesh
Embedded Systems

13. PROGRAMMABLE TIMER AND GENERAL PURPOSE IO PORTS
ADSP has 2 independent timer blocks and they perform the following
Pulse width generation
Pulse count and capture
In pulse width generation mode it can generate a modulated waveform with an arbitrary pulse width with in 71.5 secs
In pulse counter mode it can measure either high or low pulse width and the period of input wave form.
It has 12 programmable IO pins which can function either inpout or output. They can be used for conditional branching.
PROGRAM BOOTING:
The internal memory of the ADSP can be booted up at the system power up from 8 bit EPROM, a host processor or external memory.
Selection of the host boot source is controlled by BMS|( boot memory select) and BSEL( EPROM boot ) pins.
Ch.Ramesh
Embedded Systems

14. MULTIPROCESSING:
The unified address space allows direct inter processor access of both ADSP and IOP registers.
Distributed bus arbitration logic is included on chip for simple glue less connection of systems containing a maximum of two ADSPs, and a host processor.
Master processor changeover incurs only one cycle of overhead.
A vector interrupt is provided for inter processor commands.
Maximum throughput for inter processor data transfer is 132 Mbytes /sec.
Ch.Ramesh
Embedded Systems

15. END
Ch.Ramesh
Embedded Systems