1. Chapter01 Computer System Overview
Operating System
Chapter01 Computer System Overview

2. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor
This chapter provides an overview of computer system hardware, which might be important to topics covered later.

3. 1.0 Intro(1/1) Operating System 概述
承上：Provides a set of services to system users
启下：Exploits the hardware resources of
One or more processors
Main memory
Manages I/O devices
secondary memory
Network Card …

4. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

5. 1.1 Basic Elements(1/2) Processor(处理器) Main Memory(内存)
Volatile （易失性）
referred to as real memory(实存) or primary memory（主存）
I/O modules(输入/输出模块)
secondary memory devices （disk）
communications equipment
terminals
System bus(系统总线)
communication among processors, memory, and I/O modules

6. 1.1 Basic Elements(2/2)

7. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

8. 1.2 Processor Registers(1/4)
What is Registers
Memory inside CPU
Why Registers
Enable CPU to minimize main-memory references
Can be classified into:
User-visible registers(用户可见寄存器)
Control and status registers(控制和状态寄存器)

9. 1.2 Processor Registers(2/4)
User-Visible Registers
How to use：May be referenced（访问/存取） by machine/assemble language
Who will use：Available to all programs
application programs
system programs
int f() {
register int i=0;
for(int x=0;x<100000;x++)
i++;

10. 1.2 Processor Registers(3/4)
Control and Status Registers
Function：are used to control the operation of the processor
Most are not visible to the user.
Some may be accessibly by machine instruction in control or system mode

11. 1.2 Processor Registers(4/4)
Control and Status Registers
Program Counter (PC)
Contains the address of an instruction to be fetched
Instruction Register (IR)
Contains the instruction most recently fetched
Program Status Word (PSW)
Condition codes [more detail next]
Other state-related bits, such as:
Interrupt enable/disable
Supervisor/user mode
… …

12. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

13. 1.3 Instruction Execution (1/9)
Program in memory
CPU PC IR R
Program 1
Instruction 1
Instruction n
data 1
data n M

14. 1.3 Instruction Execution (2/9)
Key point:
Program counter (PC) of CPU holds address of the instruction to be fetched next
Fetched instruction is placed in the instruction register (IR)
Program counter (PC) of CPU is incremented after each fetch

15. 1.3 Instruction Execution (3/9)
Instruction Cycle(指令周期)
The processing required for a single instruction execution

16. 1.3 Instruction Execution (4/9)
Two stages of each Instruction Execution
Processor reads/loads/Fetches instructions from memory
Processor Executes each instruction

17. 1.3 Instruction Execution (5/9)
Fetch Phase
Fetch the next instruction and store it in the instruction register
Execute Phase
The ALU or I/O unit executes the instruction
ALU does calculations
I/O unit loads or stores data between main memory and registers

18. 1.3 Instruction Execution (6/9)
The von Neumann Loop：
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
IR = memory[PC]; // fetch phase };

19. 1.3 Instruction Execution (7/9)
Types of instructions
processor-memory
processor-I/O
data processing
control

20. 1.3 Instruction Execution (8/9)
An Example
CPU PC IR AC

21. 1.3 Instruction Execution (9/9)
An Example (cont.): the process of a program execution
指令1:
指令2
指令3

22. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

23. 1.4 Interrupts 1.4.0 Introduction
1.4.1 Interrupts and the Instruction Cycle
1.4.2 Interrupt Processing
1.4.3 Multiple Interrupts
1.4.4 Multiprogramming

24. 1.4.0 Introduction (1/3) Interrupt
A mechanism by which other modules(I/O,memory) may interrupt the normal sequencing of the processor. （by textbook)
Provided to improve processor utilization
most I/O devices are slower than the processor
processor must pause to wait for device
wasteful use of the processor
interrupt和 exception概念对比
同步/异步？？

25. 1.4.0 Introduction (2/3) Classes of Interrupts (Exceptions)
Program interrupts
arithmetic overflow (Fault)
division by zero (Fault)
reference outside user's memory space (Fault)
Timer (Interrupt)
I/O interrupt (Interrupt)
Hardware failure (Abort)

26. 1.4.0 Introduction (3/3)
Flow of Control without/with Interrupts

27. 1.4 Interrupts 1.4.0 Introduction
1.4.1 Interrupts and the Instruction Cycle
1.4.2 Interrupt Processing
1.4.3 Multiple Interrupts
1.4.4 Multiprogramming

28. 1.4.1 Interrupts and the Instruction Cycle(1/2)
At the end of each cycle, processor checks for interrupts
If no interrupts  fetch the next instruction
If an interrupt is pending, suspend execution of the current program, and execute the interrupt handler
Instruction Cycle With Interrupts

29. 1.4.1 Interrupts and the Instruction Cycle(2/2)
中断点
中断点

30. 1.4 Interrupts 1.4.0 Introduction
1.4.1 Interrupts and the Instruction Cycle
1.4.2 Interrupt Processing
1.4.3 Multiple Interrupts
1.4.4 Multiprogramming

31. 1.4.2 Interrupt Processing (1/6)
Suspends the normal sequence of execution

32. 1.4.2 Interrupt Processing (2/6)

33. 1.4.2 Interrupt Processing (3/6)

34. 1.4.2 Interrupt Processing (4/6)
Interrupt Handler (ISR – interrupt Service Routine)
Whenever there is an interrupt, control is transferred to this program. It determines the nature of the interrupt and performs the necessary actions to handle it.
修改PC的值成中断服务程序首指令的地址

35. 1.4.2 Interrupt Processing (5/6)

36. 1.4.2 Interrupt Processing (6/6)
Changes in Memory and Registers for an Interrupt

37. 1.4 Interrupts 1.4.0 Introduction
1.4.1 Interrupts and the Instruction Cycle
1.4.2 Interrupt Processing
1.4.3 Multiple Interrupts
1.4.4 Multiprogramming

38. 1.4.3 Multiple Interrupts (1/4)
Q: What will happen if an I/O modules rouse a Interrupt, while the CPU is processing instruction of an ISR
That is interrupt an ISR

39. 1.4.3 Multiple Interrupts (2/4)
Method 1：Sequential interrupt processing
Disable interrupts while an interrupt is being processed
Interrupts remain pending until the processor enables interrupts
After interrupt handler routine completes, the processor checks for additional interrupts

40. 1.4.3 Multiple Interrupts (3/4)
Method 2： Nested interrupt processing
Lower-priority interrupt handler can be interrupted (nested)

41. 1.4.3 Multiple Interrupts (4/4)
An Example of Method 2

42. 1.4 Interrupts 1.4.0 Introduction
1.4.1 Interrupts and the Instruction Cycle
1.4.3 Interrupt Processing
1.4.3 Multiple Interrupts
1.4.4 Multiprogramming

43. 1.4.4 Multiprogramming(1/1) Multiprogramming(多道程序)
Processor has more than one program to execute
The sequence that the programs are executed depends on their relative priority and whether they are waiting for I/O
After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt.

44. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

45. 1.5 The Memory Hierarchy (1/5)
Major constraints in memory
capacity
speed
expense
Memory must be able to keep up with the processor
Cost of memory must be reasonable in relationship to the other components
CPU M
Disk

46. 1.5 The Memory Hierarchy (2/5)
(Speed , Price, Capacity)的不可兼得性/矛盾:
Faster access time, greater cost per bit
Greater capacity, smaller cost per bit
Greater capacity, slower access speed
What can we do?
中庸？
To use them all in the right way: Memory Hierarchy

47. 1.5 The Memory Hierarchy (3/5)
Memory Hierarchy： Three Levels
Level 1：板上存储器
Level 2：板外存储器
Level 3：离线存储器

48. 1.5 The Memory Hierarchy (4/5)
Going Down the Hierarchy
Increasing capacity
Increasing access time ( that is slow speed )
Decreasing cost per bit
Decreasing frequency of access of the memory by the processor

49. 1.5 The Memory Hierarchy (5/5)
Locality of reference(访问局部性) / Principle of locality(局部性原理)
Spatial locality (空间局部性)
Temporal locality (时间局部性)
Why it exists
for ( i = 0; i < 20; i++ ) {
for ( j = 0; j < 10; j++ )
a[i] = a[i] * j; }

50. 1.5 The Memory Hierarchy (6/6)
MMU：

51. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

52. 1.6 Cache Memory (1/7) Exploit the principle of locality
Add something cache between fast and slow memory

53. 1.6 Cache Memory (2/7)

54. 1.6 Cache Memory (3/7) Cache Principles
Contains a copy of a portion of main memory
Processor first checks cache
(Hit) If found, just use it. And do not need access to the memory
(Miss) If not found in cache, the block of memory containing the needed information is moved to the cache and delivered to the processor C

55. 1.6 Cache Memory (4/7)

56. replacement algorithm
1.6 Cache Memory (5/7)
Cache design issues
Main categories are:
cache size
block size
mapping function
replacement algorithm
write policy
number of cache levels

57. 1.6 Cache Memory (6/7) Cache size Block size Mapping function
the unit of data exchanged between cache and main memory
hit means the information was found in the cache
Mapping function
determines which cache location the block will occupy
Replacement algorithm
determines which word in the block to replace
Least-Recently-Used (LRU)

58. 1.6 Cache Memory (7/7) Problem:
Consider a memory system with the following parameters: Tc = 40ns Tm=200ns, the average time is 50ns, what is the cache hit ratio H ?
Solution:
50 = 40 H (1-H)
H = 15/16

59. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

60. 1.7 I/O Communication Techniques (1/7)
When the processor encounters an instruction relating to I/O,
it executes that instruction by issuing a command to the appropriate I/O module.
Three techniques are possible for I/O operations:
Programmed I/O
Interrupt-Driven I/O
Direct Memory Access / DMA
CPU M
I/O

61. 1.7 I/O Communication Techniques (2/7)
Method1: Programmed I/O (可编程I/O)
I/O module performs the action, not the processor
I/O module sets appropriate bits in the I/O status register
Processor checks status until operation is complete
Disadvantage: It is a time- consuming process that keeps the processor busy needlessly.

62. 1.7 I/O Communication Techniques (3/7)
Method2: Interrupt-Driven I/O
Processor is interrupted when I/O module ready to exchange data
Processor saves context of program executing and begins executing interrupt-handler
Advantage：No needless waiting, so more efficient than programmed I/O
Disadvantage ：Still consumes a lot of processor time because every word read or written passes through the processor

63. 1.7 I/O Communication Techniques (4/7)
修改PC的值成中断服务程序首指令的地址

64. 1.7 I/O Communication Techniques (5/7)… An In
Exception
Handler (ISR)
PC= An
INTR
An+1
In+1 … …
IR= In Ax Ix
ETR
NMI
Ax+1 …
iret
CPU … …
Exception Table
Exception的编号
对应编号的Exception的ISR的地址 … …
Exception
Table
ISR Address … … … M

65. 1.7 I/O Communication Techniques (6/7)
Method3: Direct Memory Access
I/O exchanges occur directly with memory without processor involvement
Processor grants I/O module authority to read from or write to memory
Relieves the processor responsibility for the exchange. Processor is free to do other things
The processor is only involved at the beginning and end of the transfer. An interrupt is sent when the task is complete
(1) Initiate Block Read
Processor
Reg
Cache
(3) Read Done,
interrupt!
Memory-I/O bus
(2) DMA Transfer
I/O
controller
Memory
disk
Disk
disk
Disk

66. 1.7 I/O Communication Techniques (7/7)
Channel I/O
A high-performance input/output (I/O) architecture
A CPU sends relatively small programs via the channel to handle I/O tasks, which complete without further intervention from the CPU
Channel architecture use a separate, independent, low-cost processor.

67. Chapter01 Computer System Overview
1.0 Intro
1.1 Basic Elements
1.2 Processor Registers
1.3 Instruction Execution
1.4 Interrupts
1.5 The Memory Hierarchy
1.6 Cache Memory
1.7 I/O Communication Techniques
1.8 Evolution of Microprocessor

68. 1.8 Evolution of Microprocessor (1/8)
Invention that brought about desktop and handheld computing
Processor on a single chip
Fastest general purpose processor
Multiprocessors
Each chip (socket) contains multiple processors (cores)

69. 1.8 Evolution of Microprocessor (2/8)
Graphical Processing Units (GPUs)
Provide efficient computation on arrays of data using Single-Instruction Multiple Data (SIMD) techniques
Used for general numerical processing
Physics simulations for games
Computations on large spreadsheets

70. 1.8 Evolution of Microprocessor (3/8)
Digital Signal Processors(DSPs)
Deal with streaming signals such as audio or video
Used to be embedded in devices like modems
Encoding/decoding speech and video (codecs)
Support for encryption and security

71. 1.8 Evolution of Microprocessor (4/8)
System on a Chip (SoC)
To satisfy the requirements of handheld devices, the microprocessor is giving way to the SoC
Components such as DSPs, GPUs, codecs and main memory, in addition to the CPUs and caches, are on the same chip

72. 1.8 Evolution of Microprocessor (5/8)
Symmetric Multiprocessors (SMP)
A stand-alone computer system with the following characteristics:
two or more similar processors of comparable capability
processors share the same main memory and are interconnected by a bus or other internal connection scheme
processors share access to I/O devices
all processors can perform the same functions
the system is controlled by an integrated operating system that provides interaction between processors and their programs at the job, task, file, and data element levels

73. 1.8 Evolution of Microprocessor (6/8)
SMP Organization

74. 1.8 Evolution of Microprocessor (7/8)
Multicore Computer
Also known as a chip multiprocessor
Combines two or more processors (cores) on a single piece of silicon (die)
each core consists of all of the components of an independent processor
In addition, multicore chips also include L2 cache and in some cases L3 cache

75. 1.8 Evolution of Microprocessor (8/8)
Intel Core i7

76. Summary Basic Elements processor, main memory, I/O modules, system bus
Instruction execution
processor-memory, processor-I/O, data processing, control
Interrupt/Interrupt Processing
Memory Hierarchy
Cache/cache principles and designs
GPUs, SIMD, DSPs, SoC
Multiprocessor/multicore

77. Homework
Review Questions:
1.4
1.9
Problems:
1.1
1.13