1. High frequency signal source with characteristics suitable for THz Applications and Measurements(VNA)
Department of Communication Engineering research group Talk
Ahmadu Bello University, Zaria. Nigeria
Bello Habeeb
April 09, 2019

2. Objective: CELTA ITN Project
CELTA is the acronym for Convergence of Electronics and Photonics Technologies for Enabling Terahertz
Objective:
CELTA aims to produce the next generation of researchers who will to take a leading role in the multidisciplinary area of utilizing Terahertz technology for applications involving components and complete systems for sensing, instrumentation, imaging, spectroscopy, and communications
CELTA ESRs are working and researching to develop demonstrators: beam steering technology for communication applications, and a THz imager for communication and sensing applications.

3. THz Beamforming
Need of ultra fast communication between end-user devices
Solution: Ultra high bandwidth indoor communication
Need for more bandwidth.
Solution: Increase the carrier frequency
Carrier frequency at mmWave range (30 – 300 GHz) suffers form large attenuation
Solution: Directive antenna
Beam alignment between devices
Solution: Beam steering

4. THz Beamforming

5. Solution: THz Imaging System Need of high resolution imaging for:
Biomedical imaging
Tumour diagnosis
Monitoring of wound healing process
Dehydration prevention by breath diagnostics.
Climate prediction
Solution:
Create a THz signal source.
imaging systems:
Camera imaging GHz

6. THz Imaging system proposed overview
Detection system
Built in CELTA
Oscillator
Power Amplifier
Multiplier
Object
Image post-processing
Availability to use implemented structures in different applications
A system suitable for 557 GHz
Phase-noise < kHz

7. THz signal source: Introduction and Motivation

8. Introduction and Motivation II

9. Design and Technology Approach

10. Technology
IHPs high performance sg13g µm BiCMOS technology with HBTs with an ft of 300 GHz and fmax at 450 GHz. The backend process offers five thin layers (from Metal 1 to Metal 5) and two thick metal layers (Top Metal 1 with thickness of 2 µm and Top Metal 2 with thickness of 3 µm)

11. A2 A1 A4 A5 A3 Layout Overview 2mm sqr A-2a A-4 A-6 A-1 A-2 A-3 A-5
A GHz Single Ended Cascode PA
A GHz Four way combined PA
A GHz Diff. VCO
A GHz Single Ended VCO
A GHz Push Push VCO

12. 183 GHz SE. VCO ( Schematic and Layout)

13. Results

14. 183 GHz Diff. VCO ( Schematic and Layout)

15. Results

16. 366 GHz Push Push VCO (schematic and layout)

17. Results Output power of -9 dBm, Tuning range of 16 GHz
Harmonic Balance
Transient
Output power of -9 dBm,  
Tuning range of 16 GHz

18. 183 GHz Single Ended Cascode PA
Layout

19. 183 GHz Single Ended Cascode PA
Schematic
PA core: Cascode Topology
Single Ended input and output
VCC=3.3 V, VCC1=VCC2=4 V, All stages in Class A biasing
C1 = 200 fF
Q1~4 = Emitter finger 8, R1 = 500 Ω, R2=300 Ω, R3=10 Ω

20. 183 GHz SE PA results Small signal simulation results
Large signal results

21. 183 GHz Four way combined PA
Layout

22. A-2. 4-way Combined PA schematic

23. 183 GHz Four way PA results Small signal simulation results
Large signal results

24. Simulated results overview

25. Switchable Low Noise Amplifiers (LNA)

26. Layout of 5 GHz Switchable LNA
Input signal (5
-10 dBm)
Switchable
Output signal
0-3 V Square wave
50 MHz
3 V VDC

27. Simulated Results The above graphs show that
Stability (k) Factor is > 1 at all frequencies
Noise figure is less than 1.07 dB
Gain is appx GHz

28. Switchable capability
Measurements Setup
S-parameters
measurement
Switchable capability
measurement

29. Simulated vs. measured S21
The graph above show the simulated and measured S21 are in agreement GHz

30. Switchable Capability
Simulated results
In pink we have the input square
wave 50 MHz, 3v
In blue we have the output
swithable 5GHz
Measured results
In blue we have the input square
wave 50 MHz, 3v
In pink we have the output
swithable 5GHz

31. G Band THz Voltage Network Analysers for chip characterisation

32. 240-GHz 1-Port VNA System – Proposed Basic Block Diagram
Freq. X4 PA
Freq. X2
PIN = ~4 dBm
fIN = ~30 GHz
LO Chain ~240 GHz
Meas. IF
𝑺 𝟏𝟏 = 𝐌𝐞𝐚𝐬. 𝐈𝐅 𝐑𝐞𝐟. 𝐈𝐅
RF Chain ~240 GHz
Ref. IF
Reference Plane
RFOUT
Cal-Kit
DUT
Architecture for 240-GHz 1-port VNA system
1-port calibration with waveguide calibration kit via RF probe
S11 measurement of DUT via RF probe

33. 240-GHz 2-Port VNA System - Basic Block Diagram
DUT
Freq. X4 PA
Freq. X2
PIN = ~4 dBm
fIN = ~30 GHz
LO Chain ~240 GHz
Meas. IF1
𝑺 𝟏𝟏 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟏 𝐑𝐞𝐟. 𝐈𝐅𝟏
𝑺 𝟐𝟏 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟐 𝐑𝐞𝐟. 𝐈𝐅𝟏
RF Chain ~240 GHz
Ref. IF1
Ref. IF2
𝑺 𝟏𝟐 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟏 𝐑𝐞𝐟. 𝐈𝐅𝟐
𝑺 𝟐𝟐 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟐 𝐑𝐞𝐟. 𝐈𝐅𝟐
Meas. IF2
Architecture for 240-GHz 2-port VNA system

34. 240-GHz 2-Port VNA System - Basic Block Diagram
DUT
Freq. X4 PA
Freq. X2
PIN = ~4 dBm
fIN = ~30 GHz
LO Chain ~240 GHz
Meas. IF1
𝑺 𝟏𝟏 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟏 𝐑𝐞𝐟. 𝐈𝐅𝟏
𝑺 𝟐𝟏 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟐 𝐑𝐞𝐟. 𝐈𝐅𝟏
RF Chain ~240 GHz
Ref. IF1
Ref. IF2
𝑺 𝟏𝟐 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟏 𝐑𝐞𝐟. 𝐈𝐅𝟐
𝑺 𝟐𝟐 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟐 𝐑𝐞𝐟. 𝐈𝐅𝟐
Meas. IF2
Architecture for 240-GHz 2-port VNA system

35. 240-GHz RF Multiplier Chain: 120-GHz Freq. Quadrupler Chain (i)
30-GHz Spiral Marchand Balun Schematic & Layout
30-GHz Balun Simulated Results
120-GHz frequency quadrupler chain
30-GHz spiral marchand balun GHz Gilbert-cell based quadrupler GHz 1- stage cascode amplifier
30-GHz spiral marchand balun
Insertion loss: ~2.5 dB (20–40 GHz)
Gain imbalance: ±0.5 dB (10–50 GHz)
Phase imbalance: ±2.5º (10–50 GHz)

36. 240-GHz RF Multiplier Chain: 120-GHz Freq. Quadrupler Chain (ii)
@PIN = 4 dBm
120-GHz Quadrupler (Left) and 120-GHz Amplifier (Right) Schematic
120-GHz Quadrupler & Amplifier Simulated Harmonics
120-GHz frequency quadrupler chain
30-GHz spiral marchand balun GHz Gilbert-cell based quadrupler (Qn,p: nonlinear tripler + Q1–4: mixer) GHz 1-stage cascode amplifier
120-GHz quadrupler & amplifier
RF output power: –1 to 3 dBm (108–136 GHz)
Harmonic rejection: >20 dB (108–136 GHz)

37. 240-GHz RF Multiplier Chain: 240-GHz Frequency Doubler
@PIN = 0 dBm
@fIN = 240 GHz
240-GHz Doubler Schematic
240-GHz Doubler Simulated Return Loss/POUT
240-GHz Doubler Simulated Conv. Gain/POUT
240-GHz frequency doubler
Gilbert-cell doubler
Common-mode degeneration with Rdeg
Simulated results
Maimum output power: 0 = 3 V, fIN = 240 GHz, PIN = 8 dBm
RF output power: –8 to –6 dBm (220–260 = 3 V, PIN = 0 dBm

38. 240-GHz RF Multiplier Chain: Simulation Results
RF Output Power
Harmonic Rejection
7th
6th
Output Power (dBm)
Output Power (dBm)
5th
@PIN = 0 dBm
@PIN = 0 dBm
Frequency (Hz)
Frequency (Hz)
240-GHz RF multiplier chain (x8)
30-GHz spiral marchand balun GHz Gilbert-cell based quadrupler GHz 1-stage cascode amplifier GHz Gilbert-cell doubler
RF output power: –17 to –15 dBm (220–260 = 2 V for 240-GHz freq. doubler
Harmonic rejection: >25 dB (220–260 GHz)

39. 240-GHz LO Multiplier Chain: 240-GHz Wilkinson Divider
S-Parameters (dB)
S32 P2 P3
Frequency (GHz)
240-GHz Wilkinson Divider layout
240-GHz Wilkinson Divider Simulated S-Parameters
240-GHz Wilkinson divider
Differential in-phase power splitter
Simulated results
Insertion loss: ~0.9 dB (220–260 GHz)
Isolation: >14 dB (220–260 GHz)
Gain imbalance: <0.4 dB (220–260 GHz)
Phase imbalance: ~3º (220–260 GHz)

40. 240-GHz LO Multiplier Chain: 240-GHz Cascode Amplifier
240-GHz Cascode Amplifier Schematic
240-GHz Cascode Amplifier S-Parameters
240-GHz cascode amplifier
3-stage cascode amplifier
Guanella transformers for I/O matching network
Simulated/measured results
Gain (S21): 5–10 dB (220–260 GHz)
Saturated output power: ~1 dBm (220–260 GHz)

41. 240-GHz LO Multiplier Chain: Simulation Results
RF Output Power
Harmonic Rejection
7th
6th
Output Power (dBm)
Output Power (dBm)
5th
@PIN = 0 dBm
* For 1 Channel
Frequency (Hz)
Frequency (Hz)
240-GHz LO multiplier chain (x8)
30-GHz spiral marchand balun GHz Gilbert- cell based quadrupler GHz 1-stage cascode amplifier GHz Gilbert-cell doubler GHz 3-stage cascode amplifier GHz Wilkinson divider + two 240-GHz 3-stage cascode amplifiers
RF output power: ~1 dBm (220–260 GHz)
Harmonic rejection: >20 dB (220–260 GHz)

42. 240-GHz Receiver Channel: 240-GHz Down-Conversion Mixer
fLO = 240 GHz, PLO = 0 dBm, Diff. IF Output
240-GHz Down-Conversion Mixer Schematic
*IF buffer excluded
240-GHz Down-Conversion Mixer Simulated Results
*Old ver.  Performance of new ver. slightly different
240-GHz down-conversion mixer
Gilbert-cell based mixer w/o Gm stage
TIA load & DC offset canc. loop for wide bandwidth and low noise figure
Simulated results
Conversion gain: ~12 dB (200–270 GHz)
SSB noise figure: ~13 dB (200–270 GHz)

43. 240-GHz Receiver Channel: Simulation Results
Conversion Gain
Linearity
IF Output Power (dBm)
Conversion Gain (dB)
@RF PIN = -30 dBm
Frequency (Hz)
RF Input GHz (dBm)
*IF fixed to 1.1 GHz
*Single-ended output  3 dB less power than diff. output
*External DC blocking capacitor required for IF output
240-GHz heterodyne Rx
240-GHz Gilbert-cell based down conversion mixer with TIA load + 2-stage IF buffer
Conversion gain: >10 dB (220–260 GHz)
Input P1dB: ~–12 dB

44. 240-GHz Directional Coupler: Simulation Results
RF In (P1)
RF Out (P2)
S31
S-Parameters (dB)
S41
RF Coupled (P3)
Isolated (P4)
Frequency (GHz)
240-GHz directional coupled line coupler
Insertion loss (–S21): ~1 dB (200–300 GHz)
Coupling coefficient (–S31): ~10 dB (200–300 GHz)
Isolation (–S41): >30 dB (200–300 GHz)
Directivity (S31–S41): ~20 dB (200–300 GHz)

45. 240-GHz 1-Port VNA: Reflection Simulation Results
Open Load
Open Load
Open Load
Ref. IF POUT (dBm)
Meas. IF POUT (dBm)
Reflection (dB)
50 Ohm Load
50 Ohm Load
50 Ohm Load
RF Freq. (Hz)
RF Freq. (Hz)
RF Freq. (Hz)
Freq. X4 PA
Freq. X2
Meas. IF
𝑺 𝟏𝟏 = 𝐌𝐞𝐚𝐬. 𝐈𝐅𝟏 𝐑𝐞𝐟. 𝐈𝐅𝟏
Ref. IF
50 Ω
Open
Reflection simulation results with open and 50 ohm load

46. 240-GHz 1-Port VNA: Layout 1.8 mm RF Out Dir. Coupler 1 Dir. Coupler 2
Meas. Rx
Ref. Rx
2.3 mm
RF Chain
LO Chain
RF In / Ref. IF Out / LO In / Meas. IF Out

47. 240-GHz 1-Port VNA: Pad Information
IFOUT2
LOIN
IFOUT1
RFIN Va Vb Vc Vd Ve Vf
RFOUT
Pad
Description V1
LO 120-GHz Quadrupler VCC = 3 V V2
LO 240-GHz Doubler VB = 3 V V3
LO 240-GHz Doubler VCC = 3 V (POUT = ~–6 dBm) V4
LO 120-GHz Quadrupler Output Buffer VCC = 3 V V5
LO 240-GHz Amplifier VCC = 3 V V6
LO Ref. Rx 240-GHz Amplifier VCC = 3 V V7
RF 120-GHz Quadrupler VB = 0.88 V V8
RF 120-GHz Quadrupler VCC = 3 V V9
RF 120-GHz Quadrupler Output Buffer VCC = 3 V
V10
RF 240-GHz Doubler VB = 3 V
V11
RF 240-GHz Doubler VCC = 2 V (POUT = ~–15 dBm) Va
Ref. Rx 240-GHz LO Input Buffer VCC = 3.3 V Vb
Ref. Rx 240-GHz Mixer VB/DC Offset Cancel Loop VDD/TIA VCC/IF Amp. VCC = 3.3 V (Mixer VCC Provided by DC Offset Cancel Loop) Vc
Meas. Rx 240-GHz Mixer VB/DC Offset Cancel Loop VDD/TIA VCC/IF Amp. VCC = 3.3 V (Mixer VCC Provided by DC Offset Cancel Loop) Vd
Meas. Rx 240-GHz LO Input Buffer VCC = 3.3 V Ve
LO Meas. Rx 240-GHz Amplifier VCC = 3 V Vf
LO 120-GHz Quadrupler VB = 0.88 V
RFIN
RF Input = ~27–33 GHz, 0 dBm (Excluding Probe/Pad Loss)
IFOUT1
Ref. Rx IF Output (Single-Ended, DC Block Cap Required) = 0–20 GHz
LOIN
LO Input = ~27–33 GHz, 0 dBm (Excluding Probe/Pad Loss)
IFOUT2
Meas. Rx IF Output (Single-Ended, DC Block Cap Required) = 0–20 GHz
RFOUT
RF Output (RF Pad to RF Probe and DUT) = ~220–260 GHz

48. 240-GHz 1-Port VNA Test Structures: Layout
Rx w/ LO Chain Rx
LO Chain
Dir. Coupler
S31
Dir. Coupler
Thru
Dir. Coupler
Line
Dir. Coupler
S21
Dir. Coupler
S41
Dir. Coupler
Reflect

49. 240-GHz 1-Port VNA Test Structures: Pad Information
LOIN
RFIN G G G
RFC G
IFOUT1
IFOUT2 G G G G
RFC
RFC
RFC
RFC G G G
RFC G G G G G G G G G
RFC
RFC
RFC G G G
RFC
RFC G G G
RFC G G G
Pad
Description V1
LO 120-GHz Quadrupler VB = 0.88 V V2
LO 120-GHz Quadrupler VCC = 3 V V3
LO 120-GHz Quadrupler Output Buffer VCC = 3 V V4
LO 240-GHz Doubler VB = 3 V V5
LO 240-GHz Doubler VCC = 3 V V6
LO 240-GHz Amplifier VCC = 3 V V7
Rx 240-GHz LO Input Buffer VCC = 3.3 V
Pad
Description V8
Rx 240-GHz Mixer VB/DC Offset Cancel Loop VDD/TIA VCC/IF Amp. VCC = 3.3 V (Mixer VCC Provided by DC Offset Cancel Loop)
LOIN
LO Input = ~27–33 GHz, 0 dBm (Excluding Probe/Pad Loss)
RFIN
RF Input = ~220–260 GHz, –30 to –10 dBm (Excluding Probe/Pad Loss, For Input P1dB Measurement)
IFOUT1
(+) IF Output (DC Block Cap Required) = 0–20 GHz (IFOUT1,2 Differential Output)
IFOUT2
(-) IF Output (DC Block Cap Required) = 0–20 GHz (IFOUT1,2 Differential Output)
RFC
RF Input/Output for Directional Coupled Line Couplers

50. Appendix: 176 GHz Diff VCO

51. Appendix: 192 GHz and 384 GHz Paper

52. Bello Habeeb
294
777