1. 102-1 Under-Graduate Project: RTL Coding Style
Speaker:黃乃珊
Adviser: Prof. An-Yeu Wu
Date: 2013/12/12

2. Outline Principles of RTL Coding Styles Debugging Tool: nLint
Readability
Finite state machine (FSM)
Coding for synthesis
Partitioning for synthesis
Debugging Tool: nLint

3. Pre-RTL Preparation Checklist
Communicate design issues with your teammates
Naming conventions, directory trees and other design organizations
Have a specification for your design
Everyone should have a specification BEFORE they start coding
Design partition
Follow the specification’s recommendations for partition
Break the design into major functional blocks
1. Discuss with teammates
2. Maybe timing constraint, throughput, I/O
Design partition: divide and conquer

4. RTL Coding Style
Start
Cmpt
End
haha55
yaya66
Sum_2
Multiply_0
Create a block level drawing of your design before you begin coding.
Draw a block diagram of the functions and sub-functions of your design.
Hierarchy design
Always think of the poor guy who has to read your RTL code.
Easy to understand.
Meaningful names.
Comments and headers.

5. Outline Principles of RTL Coding Styles Debugging Tool: nLint
Readability
Finite state machine (FSM)
Coding for synthesis
Partitioning for synthesis
Debugging Tool: nLint
Coding for readability
Focusing on lexical conventions and basic RTL constructs
Coding for portability
create code that is technology-independent, compatible with various simulation tools
Guidelines for clocks and resets …
Coding for synthesis
achieve the best compile times and synthesis results, including:
testability, performance, simplification of static timing analysis, gate-level circuit behavior that matches that of the original RTL code
Partitioning for Synthesis
Better synthesis results
Faster compile runtimes
Ability to use simpler synthesis strategies to meet timing

6. File Headers
Include informational header at the top of every source file, including scripts.
Filename
Author information, e.g. name, …
Description of function and list of key features of the module
Available parameters
Reset scheme and clock domain
Date the file was created and modified
Critical timing and asynchronous interface
A corporation-wide standard template

7. File Header Example: DCT.v

8. Identifiers Naming Rule
Begin with an alpha character (a-z, A-Z) or an underscore (_) and can contain alphanumeric, dollar signs ($) and underscore.
Examples of illegal identifiers:
34net
a*b_net
Up to 1023 characters long
Case sensitive
e.g. sel and SEL are different identifiers

9. General Naming Conventions(1/3)
Lowercase letters for all signals, variables, and port names.
reg is used in procedural block
Uppercase letters for constants and user-defined types.
e.g. `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names
Use ram_addr for RAM address bus instead of ra
Develop, document, and use a naming convention consistently throughout a design.

10. General Naming Conventions(2/3)
Use clk for the clock signal
If more than one clock, use clk as the prefix for all clock signals (clk1, clk2, clk_interface)
For active low signals, use *_n
If the reset signal is active low, use rst_n
Similarly, for active high signals, use *_p
For input of a register, use *_w
For output of a register, use *_r
For input signals, use *_i
For output signals, use *_o

11. Example Reg1 Com. Logic Reg2 Top For connection Logic data_i reg1_w
assign reg1_w = data_i;
assign reg2_w = com1_o;
assign com1_i = reg1_r;
(posedge clk_p) begin
reg1_r <= reg1_w;
reg2_r <= reg2_w;
end
begin
com1_o = com1_i + 4’d5;
data_i
reg1_w
reg1_r
com1_i
com1_o
data_o
Reg1
Com. Logic
reg2_w
reg2_r
Reg2
Top
For connection
Logic

12. General Naming Conventions(3/3)
Use [x:0] (instead of [0:x]) when describing multi-bit buses
A somewhat arbitrary suggested “standard”
Use parameter to improve readability
module car (out, in1, in2);
…………
parameter S0_STOP = 2’d0, S1_RUN = 2’d1;
case (state) S0_STOP:
…..
Don’t use HDL reserved words
e.g. xor, nand , module
Use a consistent ordering helps improve the readability of the code and reduce s the chance of accidentally swapping order between connected buses

13. Use comments Use comments appropriately to explain
Brief, concise, explanatory
Avoid “comment clutter”– obvious functionality does not need to be commented
Single-line comments begin with //
Multiple-line comments start with /* and end with */
Use indentation to improve the readability of continued code lines and nested loops
e.g.

14. Module Instantiation
Always use explicit mapping for ports, use named mapping rather than positional mapping
module_a (
clk,
s1_i,
s1_o,
s2_i,
s2_o );

15. Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization
for example:

16. Outline Principles of RTL Coding Styles Debugging Tool: nLint
Readability
Finite state machine (FSM)
Coding for synthesis
Partitioning for synthesis
Debugging Tool: nLint
Coding for readability
Focusing on lexical conventions and basic RTL constructs
Coding for portability
create code that is technology-independent, compatible with various simulation tools
Guidelines for clocks and resets …
Coding for synthesis
achieve the best compile times and synthesis results, including:
testability, performance, simplification of static timing analysis, gate-level circuit behavior that matches that of the original RTL code
Partitioning for Synthesis
Better synthesis results
Faster compile runtimes
Ability to use simpler synthesis strategies to meet timing

17. Finite State Machines
FSM have widespread application in digital systems.
Most frequently used in controller
Mealy Machine: The next state and the outputs depend on the present state and the inputs.
Moore Machine: The next state depends on the present state and the inputs, but the output depends on only the present state.
output = f (In, CS)
output = f (CS)

18. Modeling FSM in Verilog
Sequential Circuits
Memory elements of States (S)
Combinational Circuits
Next-state Logic (NL)
Output Logic (OL)
Three coding styles
(1) Separate S, OL and NL
(2) Combines NL+ OL, separate S
(3) Combine S + NL, separate OL 􀃎
Not recommended!!
Mix the comb. and seq. circuits

19. Style (1) Separate S, NL, OL

20. Style (2) Combine NL+OL; Separate S

21. Outline Principles of RTL Coding Styles Debugging Tool: nLint
Readability
Finite state machine (FSM)
Coding for synthesis
Partitioning for synthesis
Debugging Tool: nLint
Coding for readability
Focusing on lexical conventions and basic RTL constructs
Coding for portability
create code that is technology-independent, compatible with various simulation tools
Guidelines for clocks and resets …
Coding for synthesis
achieve the best compile times and synthesis results, including:
testability, performance, simplification of static timing analysis, gate-level circuit behavior that matches that of the original RTL code
Partitioning for Synthesis
Better synthesis results
Faster compile runtimes
Ability to use simpler synthesis strategies to meet timing

22. Reset Signal Use the reset signal to initialize registered signals
dct_r <= 1’b0;
dct_r <= dct_w;
Do not use an initial statement to initialize the signal

23. Avoid Latches (1/2) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles
Latch inferred because of missing else condition
Latches inferred because of missing assignments and missing condition
As an exception, you can instantiate technology-independent GTECH D latches. However, all latches must be instantiated and you must provide documentation that lists each latch and describes any special timing requirements that result from the latch.
Register files, memories, FIFOs, and other storage elements are examples of situations in which D latches are permitted.

24. Avoid Latches (2/2) Avoid inferred latches
Fully assign outputs for all input conditions

25. Avoid Combinational Feedback
Combinational feedback cause making accurate static timing analysis very hard.

26. Sensitivity List (1/3)
For combinational blocks, the sensitivity list must include every signal that is read by the process.
Signals that appear on the right side of an assign statement
Signals that appear in a conditional expression
For simplicity, Verilog 2001 supports (*)

27. Sensitivity List (2/3)
Include a complete sensitivity list in each of always blocks
If not, the behavior of the pre-synthesis design may differ from that of the post-synthesis netlist.

28. Sensitivity List (3/3) For sequential blocks
The sensitive list must include the clock signal.
If an asynchronous reset signal is used, include reset in the sensitivity list.
Use only necessary signals in the sensitivity lists
Unnecessary signals in the sensitivity list slow down simulation

29. Combinational vs. Sequential Blocks
Combinational logic
Use blocking (=) assignments
Execute in sequential order
Sequential logic
Use nonblocking (<=) assignments
Execute concurrently
Do not make assignments to the same variable from more than one always block. Multiple Assignment + A B C
sum_1
sum_2
begin
sum_1 = A + B;
sum_2 = sum_1 + C;
end
m1_w
m1_r
clk
clk) begin
m1_r <= m1_w;
m2_r <= m2_w;
end
m2_w
m2_r
clk

30. case Statement
Fully specified verilog case statements result in a single-level multiplexer
Partially specified Verilog case statements result in latches
case (sel)
2’b00: outc = a;
2’b01: outc = b;
2’b10: outc = c;
default: outc = d;
endcase;

31. if-then-else Statement
An if-then-else statement infers a priority-encoded, cascaded combination of multiplexers.
if (sel == 2’b00)
outi = a;
else if (sel = 2’b01)
outi = b;
else if (sel = 2’b10)
outi = c;
else
outi = d;

32. case vs. if-then-else Statements
case statements are preferred if the priority-encoding structure is not required
The multiplexer is faster.
if-then-else statement can be useful if you have a late-arriving signal
Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer.
assign z = (sel_a) ? a : b;
In a cycle-based simulator, the case statement simulates faster than the if-then-else statement.
For large multiplexers, a case statement will simulate faster than a conditional assignment on most simulators, and especially on cycle-based simulators.

33. Outline Principles of RTL Coding Styles Debugging Tool: nLint
Readability
Finite state machine (FSM)
Coding for synthesis
Partitioning for synthesis
Debugging Tool: nLint
Coding for readability
Focusing on lexical conventions and basic RTL constructs
Coding for portability
create code that is technology-independent, compatible with various simulation tools
Guidelines for clocks and resets …
Coding for synthesis
achieve the best compile times and synthesis results, including:
testability, performance, simplification of static timing analysis, gate-level circuit behavior that matches that of the original RTL code
Partitioning for Synthesis
Better synthesis results
Faster compile runtimes
Ability to use simpler synthesis strategies to meet timing

34. Register All Outputs
For each subblock of a hierarchical macro design, register all output signals from the subblock.
Makes output drive strengths and input delays predictable
All the inputs of each block arrive with the same relative delay.
Output drive strength is equal to the drive strength of the average flip-flop.

35. Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module R1 A B C R2
Bad
clk
clk R1
ABC R2
Better
Synthesis tools cannot move logic across hierarchical boundaries during default compile operations
Improved sequential mapping during optimization because no hierarchical boundaries exist between the sequential logic and the combinational logic that drives it.
clk
clk R1
ABC R2
Best
clk
clk

36. Outline Principles of RTL Coding Styles Debugging Tool: nLint
Readability
Finite state machine (FSM)
Coding for synthesis
Partitioning for synthesis
Debugging Tool: nLint
Coding for readability
Focusing on lexical conventions and basic RTL constructs
Coding for portability
create code that is technology-independent, compatible with various simulation tools
Guidelines for clocks and resets …
Coding for synthesis
achieve the best compile times and synthesis results, including:
testability, performance, simplification of static timing analysis, gate-level circuit behavior that matches that of the original RTL code
Partitioning for Synthesis
Better synthesis results
Faster compile runtimes
Ability to use simpler synthesis strategies to meet timing

37. GUI
nLint -gui &

38. Import Design

39. Edit File

40. Lint -> Run

41. Fix Warning 1

42. Search Rule
Right click -> Search Rule

43. No Error & Warning

44. Check for Synthesizable (1/2)
SpringSoft nLint
Check for correct mapping of your design
Not so power in detecting latches
Synopsys Design Compiler
Synthesis Tool
The embedded Presto Compiler can list your flip-flops and latches in details
> dv -no_gui
> read_verilog yourdesign.v

45. Check for Synthesizable (2/2)
Checking latches using Design Compiler