1. VME64x Digital Acquisition Board
Architecture
(DAB64x)
Stratix
FPGA
VME
Sync.
SRAM
Timing
Clock
12-bit
Mezzanine
12-bit
Mezzanine
Main Features
FPGA Core: Altera Stratix EP1S10… EP1S40F780
Synchronous SRAM: 3 blocks of 128K…2M  32/36
2  12 bits Mezzanine Boards for specific acquisition functions
VME Access: D32/A32 or D64/A64
Timing and Acquisition Clock management
JL Gonzalez

2. VME64x Digital Acquisition Board
(TRIUMF-DAB64x)
Designed to handle 2 channels of 12-bit 40MHz Data
Will be used for LTI and LHC beam position system; SPS, LTI and LHC fast beam intensity measurements and LHC beam loss system
JL Gonzalez

3. P0 - Connector JL Gonzalez Pin Row a Row b Row c Row d Row e Row f 1
BLMin1
-5V2RET
Capture Start
Post Mortem Start
GND 2
BLMin2
Auxiliary d2
Post Mortem Freeze 3
BLMin3
Auxiliary d3
Auxiliary PM Start 4
BLMin4
-5V2
Auxiliary d4
Auxiliary PM Freeze 5
BLMout1
Auxiliary d5
Orbit Start 6
BLMout2
Auxiliary d6
Auxiliary e6 7
BLMout3
-2VRET
Auxiliary d7
Auxiliary e7 8
BLMout4
Auxiliary d8
Auxiliary e8 9
Unused
-2V 10 11 12
+5V
BS0
LVDS Turn clock Delay + 13
BS1
LVDS Turn clock Delay - 14
+5VRET
BS2 15
BS3 16
+15V
BS4
LVDS 40 MHz Clock + 17
+15VRET
BS5
LVDS 40 MHz Clock - 18
-15VRET
BS6 19
-15V
BS7
JL Gonzalez

4. Main Devices - Stratix EP1S…
Altera FPGA:
Stratix Overview: 1.5 V Pin FineLine BGA
EP1S20
EP1S30
EP1S40
Logic Elements (LEs)
18 460
32 470
41 250
M512 RAM blocks (32 x 18 bits)
194
295
384
M4K RAM blocks (128 x 36 bits) 82
171
183
M-RAM blocks (4K x 144 bits) 1 4
Total RAM bits
DSP blocks 10 12 14
Embedded multipliers (9x9-bit) 80 96
112
PLLs 6
Maximum user I/O pins
586
597
615
Estimated cost (EUR)
212
422
The pin out compatibility of these devices allows for different board implementations and makes the DAB64x a very versatile module
Associated memory estimated costs:
3  128K  32: 12 EUR
3  2M  36: 420 EUR
JL Gonzalez

5. Boundary Scan Test PC BS Device
JTAG
Controller PC
Power Supplies
Test Setup
BS Device P1 P0 P2
Scan Bridge
SCANSTA111
Other BS
Devices
Aux.
Mezzanine
Aux.
Mezzanine
DAB64x
During production, this test should prevent mounting or soldering errors
JL Gonzalez

6. DAB Production Schedule
History
DAB64x specs finalised in January 2003
FPGA – ALTERA Stratix
30 DABIII cards needed for in 2004
Production and testing will be done at CERN
2004
Order of main components
Tender for most expensive parts
Spring 2004: production of 3 BPM-type and 2 BLM-type prototypes (Daryl Bishop).
Tests at CERN (Daryl)
Tender for full production
Autumn 2004: pre-series production (35 modules)
2005
Full production
Tests at CERN
Installation
JL Gonzalez