1. UNIT-III
Logic Gates and other Complex gates, Switch logic, Alternate gate circuits
Physical Design, Floor Planning, Placement – Routing, Power Delay Estimation, Clock and Power Routing

2. Complementary CMOS logic gates
Logic Gates: AND,OR, NOT, NAND ,NOR ,XOR and XNOR
Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
X (crowbar)
Pull-down ON 1
Z (float)
Pull-down OFF
Pull-up ON
Pull-up OFF

3. CMOS Gate Design
A 4-input CMOS NOR gate

4. Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON

5. Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel

6. Compound Gates Compound gates can do any inverting function
Ex: AND-AND-OR-INV (AOI22)

7. Example: O3AI

8. Switch logic(Pass Transistors):
Transistors can be used as switches

9. Pass Transistors
Transistors can be used as switches

10. correspond to logic levels. VDD
Figure 3 How voltages
correspond to logic levels.
VDD
logic 1 VH
unknown (X) VL
VSS
logic 0

11. Signal Strength Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus NMOS are best for pull-down network
Thus PMOS are best for pull-up network

13. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well

14. Alternate gate circuits:
Other Forms of CMOS Logic (or)
Alternate gate circuits:
Pseudo-nMOS logic:
Pseudo-nMOS Nand gate.

15. Pseudo-nMOS Inverter when driven from a similar Inverter.

16. DCVS Logic(Differential cascode voltage switch logic):
out
out’
pulldown
network -
complementary
pulldown
inputs
network -
inputs

17. a'b'+a'c'
(a+bc)' b a’ a c c' b'
Figure : shows the circuit for a particular DCVSL gate. This gate
computes a+bc on one output and (a+bc)’ = a’b’+a’c’ on its other
output.

18. Dynamic CMOS logic:
Dynamic CMOS logic three-input Nand gate

19. Clocked CMOS logic:
Clocked CMOS (C2MOS) logic

20. CMOS domino logic:
Charge sharing in a domino circuit

21. Physical Design

23. Physical design – overall flow
Partitioning
Floorplanning
Placement
Improvement
Cost Estimation
Routing Region
Definition
Global Routing
Improvement
Cost Estimation
The next step in the physical design flow is the floorplanning algorithm. The output of partitioning is fed to the floorplanning algorithm.
Detailed Routing
Improvement
Cost Estimation
Compaction/clean-up
Write Layout Database

24. What is Backend? Physical Design: FloorPlanning : Architect’s job
Placement : Builder’s job
Routing : Electrician’s job

25. Physical Design Partitioning Routing Fabrication Floorplanning &
Circuit Design
Partitioning
Floorplanning
&
Placement
Routing
Fabrication

26. Package Types Through-hole vs. surface mount
21: Package, Power, and Clock

27. Chip-to-Package Bonding
Traditionally, chip is surrounded by pad frame
Metal pads on 100 – 200 mm pitch
Gold bond wires attach pads to package
Lead frame distributes signals in package
Metal heat spreader helps with cooling

28. Partitioning: Decompose a large complex system into smaller subsystems
Decompose hierarchically until each subsystem is of manageable size
Design each subsystem separately to speed up the process
Minimize connection between two subsystems to reduce interdependency
Let us start with partitioning. So the idea is to decompose a large complex system into smaller subsystem. One can either you a hierarchical partitioning or flat partitioning. This partitioning is performed until each subsystem is of manageable size – in short a divide and conquer strategy. Each subsystem can then we designed separately. This speeds up the process. One important constraint while partitioning a system is to minimize the number of connections between two subsystems. This reduces any interdependency between the two subsystems.

29. So, what is Partitioning?
System
System Level Partitioning
PCBs
Board Level Partitioning
Chips
Chip Level Partitioning
Subcircuits
/ Blocks

30. Hierarchical Design Several blocks after partitioning: Need to:
Put the blocks together.
Design each block.

31. Hierarchical Design
How to put the blocks together without knowing their shapes and the positions of the I/O pins?
If we design the blocks first, those blocks may not be able to form a tight packing.

32. Partitioning methods Top-down partitioning Bottom-up clustering
Iterative improvement
Spectral based
Clustering methods
Network flow based
Analytical based
Multi-level
Bottom-up clustering
Unit delay model
General delay model
Sequential circuits with retiming
Various algorithms have been proposed since 1969 to partition a system. You can either adopt a top-down partitioning approach or a bottom-up clustering approach. Each new partitioning algorithm adopts different strategies like the iterative improvement which goes through several iterations, or say the analytical method which adopts a mathematical approach to solve the partitioning problem. Depending on the system the objective is changed accordingly.

33. Floorplanning:
The floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize the circuit performance
chip area
total wirelength
delay of critical path
routability
others, e.g., noise, heat dissipation, etc.

34. Floorplanning v.s. Placement
Both determines block positions to optimize the circuit performance.
Floorplanning:
Details like shapes of blocks, I/O pin positions, etc. are not yet fixed (blocks with flexible shape are called soft blocks).
Placement:
Details like module shapes and I/O pin positions are fixed (blocks with no flexibility in shape are called hard blocks).

35. Floorplanning: Output from partitioning used for floorplanning Inputs:
Blocks with well-defined shapes and area
Blocks with approximated area and no particular shape
Netlist specifying block connections
Outputs:
Locations for all blocks
The input to the floorplanning stage is a set blocks that have well-defined shapes and area (like memory block which are highly regular), blocks which have approximate area and no particular shape (like any new architecture) and the netlist that connects the different block connections. The output of the floorplanning stage is the location of each block.

36. Floorplanning problem
Objectives
Minimize area
Reduce wirelength
Maximize routability
Determine shapes of flexible blocks
Constraints
Shape of each block
Area of each block
Pin locations for each block
Aspect ratio
The floorplanning problem can be formulated as follows, the objective of the floorplanning stage is to minimize the aggregate area of the system, reduce the wirelength, maximize the routability and determine shapes of flexible blocks. We are constrained by the shape of each block, area of each block, pin locations for each block and the aspect ratio. Here we have a sample of an optimal floorplan in terms of area and the corresponding non-optimal floorplan using the same blocks.

37. Dead space Dead space Dead space is the space that is wasted:
Minimizing area is the same as minimizing deads pace.
Dead space

38. Slicing and Non-Slicing Floorplan
One that can be obtained by repetitively subdividing (slicing) rectangles horizontally or vertically.
Non-Slicing Floorplan:
One that may not be obtained by repetitively subdividing alone.
Otten (LSSS-82) pointed out that slicing floorplans are much easier to handle.

39. Slicing floorplan sizing
General case: all modules are soft macros
Phase 1: bottom-up
Input – floorplan tree, modules shapes
Start with a sorted shapes list of modules
Perform vertical_node_sizing and horizontal_node_sizing
On reaching the root node, we have a list of shapes, select the one that is best in terms of area
Phase 2: top-down
Traverse the floorplan tree and set module locations
Let us look at a simple algorithm called slicing floorplan. The modules used for this algorithm are all soft macros that means the aspect ratio is flexible and the modules can be rotated. The algorithm is a two phase process. The first phase is the bottom-up approach. It uses the floorplan tree and the different module shapes as input. The floorplan tree is generated based on the partitioning results. Using a sorted list of modules vertical node sizing and horizontal node sizing. We will look at horizontal and vertical sizing in the next slide. On reaching the root node, we have a list of shapes and we select shapes for each node based on area. The second phase involves a top-down flow. Here we traverse the floorplan tree and set the locations for each module.

40. Sizing example
Here we have an example for vertical sizing and horizontal sizing. We have two block A and B. We need to figure out what is the best aspect ratio for each block and the least aggregate area of the two blocks. For the floorplanning step there is an upper and lower limit on the aspect ratio. For the two blocks. So as you can see from the slide different permissible aspect ratios and orientations are tried for both blocks. As you can see from the figure sizes a3 and b2 are selected.

41. Physical design – overall flow
Partitioning
Floorplanning
Placement
Improvement
Cost Estimation
Routing Region
Definition
Global Routing
Improvement
Cost Estimation
The next stage after floorplanning is placement.
Detailed Routing
Improvement
Cost Estimation
Compaction/clean-up
Write Layout Database

42. Placement
The process of arranging circuit components on a layout surface
Inputs : Set of fixed modules, netlist
Output : Best position for each module based on various cost functions
Cost functions include wirelength, wire routability, hotspots, performance, I/O pads
Now the objective for placement is obvious – arrange the your circuit components on a layout surface under certain constraints. The placement algorithms use a set of fixed modules and the netlist describing the connections between the various modules as their input. The output of the algorithms is the best possible position for each module based on various cost functions. You can have one or more cost functions depending on your designs. The cost functions include maximum total wirelength, wire routability, congestions, performance and I/O pads locations.

43. Good placement vs Bad placement*
No congestion
Shorter wires
Less metal levels
Smaller delay
Lower power dissipation
Bad placement
Congestion
Longer wire lengths
More metal levels
Longer delay
Higher power dissipation
Here we have two sample placement results. It is obvious that the one of the left is better than the one on the right. So what is good about the placement on the left and what are the implications? If you notice the IO pads for the placement on the left are distributed along the periphery, while for the placement on the right the IO pads are clustered in one place. As you can see there is no congestion for wire routing so that avoids any hotspots, we are using shorter wires which reduce area, power and delay. It also reduces the number of metal levels. On the other hand, for the bad placement we have congestion, long wire length, more delays, more metal level and higher power dissipation leading to an inefficient design.

44. Placement affects chip area:

45. Physical design – overall flow
Partitioning
Floorplanning
Placement
Improvement
Cost Estimation
Routing Region
Definition
Global Routing
Improvement
Cost Estimation
The next stage in the physical design flow is routing.
Detailed Routing
Improvement
Cost Estimation
Compaction/clean-up
Write Layout Database

46. Routing: Connect the various standard cells using wires Input: Output:
Cell locations, netlist
Output:
Geometric layout of each net connecting various standard cells
Two-step process
Global routing
Detailed routing
The routing stage connects the various standard cells of our system using wires. The routing algorithms use cell locations and netlist as the input and generate a geometric layout of each net that connects the various standard cells. The routing process is a two step process – global routing and detailed routing.

47. General Routing Paradigm
Two phases:

48. Global routing vs detailed routing
So what is the difference between global routing and detailed routing. Suppose the chip is is North America and some travelers in California need advice on how to drive from Stanford (near San Francisco) to Caltech (near Los Angeles). The floorplanner has decided that California is on the left (west) side of the ASIC and the placement tool has put Stanford in Northern California and Caltech in Southern California. Floorplanning and placement have defined the roads and freeways. There are two ways to go: the coastal route (using Highway 101) or the inland route (using Interstate I5, which is usually faster). The global router specifies the coastal route because the travelers are not in a hurry and I5 is congested (the global router knows this because it has already routed onto I5 many other travelers that are in a hurry today). Next, the detailed router looks at a map and gives indications from Stanford onto Highway 101 south through San Jose, Monterey, and Santa Barbara to Los Angeles and then off the freeway to Caltech in Pasadena. So in case of a chip, global routing generates a loose route for each net and list of routing regions are assigned, while detailed routing does the geometric layout for each net within the assigned routing regions. As you can see from this example, global routing determined the approximate routes between the various modules of the system, while detailed routing generated the geometric layout of each net.

49. Routing Regions

50. Routing problem formulation
Objective
100% connectivity of a system
Minimize area
Minimize wirelength
Constraints
Number of routing layers
Design rules
Timing (delay)
Crosstalk
Process variations
The system routing problem can be formulated as follows – the objective is to provide 100% connectivity of the system, while minimizing area and wirelength. And we are constrained by the number of metal layers, design rules like spacing between different wires, wire dimensions, timing, interconnect crosstalk and variations in the technology manufacturing process.

51. Specialized routing * © Sherwani 92
Once we have routed the signal interconnects, next we route the clocks and power lines. We talked about clock routing last week. The idea is to minimize the clock skew and the delay along the clock routing path. In case of power routing, we need to have low resistance metal lines to ensure adequate current.
* © Sherwani 92

52. Summary Looked at the physical design flow Involved several steps
Partitioning
Floorplanning
Placement
Routing
Each step can be formulated as an optimization problem
Need to go through 2 or more iterations in each step to generate an optimized solution