1. 4. Microsystem Modeling using HDLs
Spring 2009
Rajesh K. Gupta

2. Outline Design modeling Language models Orientation in HDLs
models, abstraction levels and views
hardware description languages
Orientation in HDLs
Introduction to VHDL
simple examples
VHDL Model of System
computational model, processes, timing, variables and signals
References:
Ashenden’s Book: Chapters 1-5 or equivalent

3. A Model From OED: a “model” is A model is described in some ‘terms’
a representation of structure
summary, abstraction, simplified, idealized
a description of structure
resemblance
A model is described in some ‘terms’
Mathematical terms => mathematical model
Formal terms => formal model
VHDL language => VHDL model
‘Abstract’ models?
Same as mathematical/formal models

4. Design Modeling Design representation and description in some ‘terms’
For the purpose of representation, often irrelevant details are removed from a model.
Classified in terms of
levels of abstraction: architectural, logic, geometric
choice of views: behavioral, structural, physical

5. Language Models
Programming languages are often used for constructing system models
Languages for description,simulation, synthesis of hardware
VHDL, Verilog, HardwareC, UDLI, …
Collectively referred to as Hardware Description Languages (HDLs)
Using HDLs, hardware design can often look like an exercise into programming
or is it?

6. Hardware versus Software Models
concurrency in operations
I/O ports and interconnection of blocks
exact event timing is important: open computation
Software
typically sequentially execution (model)
structural information is less important
exact event timing is not important: closed computation

7. Language Characterization
Syntax:
‘look’ of a language
defines the set of legal programs
specified by a grammar
Semantics:
specifies meaning of each syntactical structure
different ways of specifying it:
operational semantics: defines “what is to be done”
formal semantics: axiomatic or denotational
Pragmatics
implementation issues.

8. Language Types Imperative or Procedural Langauges
actions as a sequence of steps
associates names (variables) with the sequence
sequence changed by assignments
examples: VHDL, Verilog, HardwareC, Pascal
Applicative Languages
actions through application of functions and parameter binding
binding provides just a name for bound value, can not change it
repetition by recursion
examples: Lisp, Silage
In practice, this division is not so sharp
Algol, Pascal permit functional subprograms and recursion
Side effects and iterations in Lisp
Pragmatics often makes the distinction.

9. Languages for Hardware Modeling
Classified based on the view supported
Behavioral View
Mainly imperative
Structural View
Mostly declarative (with some procedural features)
Physical View
Declarative or procedural
Physical layout languages

10. Relationship to Abstractions

11. Physical and Structural Views
Physical View
composition of geometric objects
examples: CIF (declarative), L (procedural)
Structural View
interconnection of components (blocks)
similar to circuit schematics (textual description)
incidence and adjacency
hierarchy and instantiation
examples: VHDL, Verilog
Behavioral View
set of tasks with partial order relation
tasks can be generic operations (functional) or logic functions (logic)

12. HDL Issues
Functional level descriptions often use a mixture of behavioral and structural views
Meaning of variables, data-structures, multiple-assignments for variables
implementation as registers, wires, muxes
choice determined by variable semantics
multiple assignments:
last assignment or OR’ing or
sequential behavior
Timing semantics
determines relation of behavior in time with language constructs
cycle-based or event-based semantics
constructs for addressing ‘future’ events, constraints

13. Design synthesis

14. Taxonomy of Synthesis Tasks
Architectural or functional level
Source: Mani Srivastava, UCLA

15. What is Logic or Register-Transfer Level Synthesis?D Q
combinational
logic
A register-transfer system is a sequential machine
Combinational logic connecting registers
Functionality described as new values of register in a clock cycle
Depends on input and current register values
Depends on the “transfer functions” associated with the various combinational logic blocks
Register-transfer design is structural - complex combinations of state machines may not be easily described solely by a large state transition graph.
Register-transfer design concentrates on functionality, not details of logic design.
Modern VLSI Design 3e: Chapter 8, Copyright © 1998, 2002 Prentice Hall PTR

16. Register-Transfer Simulation
Simulates to clock-cycle accuracy.
Doesn’t guarantee timing.
Important to get proper function of machine before jumping into detailed logic design.
(But be sure to take into account critical delays when choosing register-transfer organization.)
We choose VHDL in this course
one of the two popular languages used for hardware modeling.
Modern VLSI Design 3e: Chapter 8, Copyright © 1998, 2002 Prentice Hall PTR

17. VHDL ADA-like syntax (DoD VHSIC project)
Philosophy: readable, documentation-based on a clear unambiguous and predictable simulation behaviora
Simulation oriented
Features:
Sequential Procedural language: PASCAL and ADA like
User defined value abstractions
Concurrency: statically allocated network of processes
Timing constructs
Discrete-event simulation semantics
Object-oriented goodies: libraries, packages, polymorphism

18. Using VHDL Design entity consists of entity IDENTIFIER is
interface
body: behavioral, structural, data-flow styles
entity IDENTIFIER is
generic INTERFACE_LIST ;
port INTERFACE_LIST;
declarations;
begin
statements;
end IDENTIFIER;
Data types
attributes
file, alias
subprogram
use clause
signal
Concurrent assertions;
concurrent procedures;
passive process;

19. Value Abstractions in VHDL
Constants
Variables
syntax: var:= expression
can be declared in body (inside process) or subprogram (outside process)
a body-declared variable is never reinitialized
a sub-program declared variable is initialized for each call to the subprogram
value assignment as immediate effect
Signals
syntax: signal <= value
delayed value assignment
optional propagation delay attribute
no global variables to avoid synchronization problems
value resolution for multiple assignments.

20. Ports entity FA is port (X, Y, Cin : in bit);
Ports can be one of five types
in read only
out update only
inout read and update (2 distinct ports)
buffer read/update, buffered, no resolution
linkage

21. Source: Mani Srivastava, UCLA
A NAND Gate Example
-- black-box definition (interface) entity NAND is generic ( Tpd : time := 0 ns ); port ( A, B : in bit; Y : out bit ); end NAND; an implementation (contents) architecture BEHAVIOR_1 of NAND is begin Y <= A nand B after Tpd; end BEHAVIOR_1;
Important Concepts entity architecture generic port waveform assignment
Source: Mani Srivastava, UCLA

22. Another Implementation of NAND
-- there can be multiple implementations architecture BEHAVIOR_2 of NAND is signal X : bit; begin -- concurrent statements Y <= X after Tpd; X <= ‘1’ when A=’0’ or B=’0’ else                    ‘0’; end BEHAVIOR_2;
Important Concepts multiple architectures signal concurrent statements
Source: Mani Srivastava, UCLA

23. Yet More NAND Gates!
entity NAND_N is generic ( N : integer := 4; Tpd : time); port ( A, B : in bit_vector(1 to N); Y : out bit_vector(1 to N)); end NAND_N; architecture BEHAVIOR_1 of NAND_N is begin process variable X : bit_vector(1 to N); begin X := A nand B; Y <= X after Td; wait on A, B; end process; end BEHAVIOR_1;
Important Concepts process variable wait sequential statements events
Source: Mani Srivastava, UCLA

24. Source: Mani Srivastava, UCLA
The process Statement
[label:] process [(sensitivity_list)] [declarations] begin {sequential_statement} end process [label];
It defines an independent sequential process which repeatedly executes its body
Following are equivalent: process (A,B) process begin begin C <= A or B; C <= A or B; end; wait on A, B; end;
No wait statements allowed in the body if there is a sensitivity_list
Source: Mani Srivastava, UCLA

25. Source: Mani Srivastava, UCLA
The wait Statement
wait   [on list_of_signals]            [until boolean_expression] [for time_expression] ;
This is the ONLY sequential statement during which time advances!
examples:
-- wait for a rising or falling edge on CLK wait on CLK; wait until CLK’EVENT; -- this is equivalent to the above wait for rising edge of CLK wait on CLK until CLK=’1’; wait until CLK=’1’; -- this is equivalent to the above wait for 10 ns wait until 10 ns; wait for ever (the process effectively dies!) wait;
Source: Mani Srivastava, UCLA

26. User Defined Attributes
Used for
any user defined information
associated with
entities, architectures, configurations, subprograms, components…
Attributes are LOCAL.
They can not be used to pass information from one description to another (such as back annotation)
For example, an architecture can not “fill in” an attribute of an entity.
entity cell is
generic (…);
port (…);
attribute Xpos, Ypos, Xsize, Ysize: integer;
attribute Xpos of entity_spec is 200;

27. Passive Processes Processes that do not update any port or signal
For example:
concurrent procedure call
concurrent assertion
entity and_gate is
port (in1, in2: in bit; out1: out bit);
begin
process
assert out1 = (in1 and in2);
end process;
end and_gate;

28. A Simple Producer-Consumer Example
Produces
DATA
Consumer
REQ
ACK
Source: Mani Srivastava, UCLA

29. Producer-Consumer in VHDL
entity producer_consumer is end producer_consumer; architecture two_phase of producer_consumer is signal REQ, ACK : bit; signal DATA : integer; begin P: process begin DATA <= produce(); REQ <= not REQ; wait on ACK; end P; C: process begin wait on REQ; consume(DATA); ACK <= not ACK; end C; end two_phase;
Source: Mani Srivastava, UCLA

30. Producer-Consumer in VHDL 4-Phase Case
architecture four_phase of producer_consumer is signal REQ, ACK : bit := ‘0’; signal DATA : integer; begin P: process begin DATA <= produce(); REQ <= ‘1’; wait until ACK=’1’; REQ <= ‘0’; wait until ACK=’0’; end P; C: process begin wait until REQ=’1’; consume(DATA); ACK <= ‘1’; wait until REQ=’0’; ACK <= ‘0’; end C; end four_phase;
Source: Mani Srivastava, UCLA

31. A Edge Triggered D Flip-Flop
entity DFF is generic (T_setup, T_hold, T_delay : time:=0 ns); port (D, CLK: in bit; Q : out bit); begin -- check setup time assert not (CLK’EVENT and CLK=’1’ and     D’LAST_EVENT < T_setup) report “Setup violation” severity WARNING; -- check hold time assert not (CLK’DELAYED(T_hold)’EVENT and     CLK’DELAYED(T_hold)=’1’ and     D’LAST_EVENT < T_hold) report “Hold violation” severity WARNING; end DFF;
Source: Mani Srivastava, UCLA

32. A Edge Triggered D Flip-Flop (contd.)
architecture BEHAVIOR of DFF is begin process begin wait on CLK until CLK=’1’; Q <= D after T_delay; end process; end BEHAVIOR;
Source: Mani Srivastava, UCLA

33. Behavior vs. Structure Description
An entity can be described by its behavior or by its structure, or in a mixed fashion
Example: a 2-input XOR gate
Source: Mani Srivastava, UCLA

34. Source: Mani Srivastava, UCLA
XOR in VHDL: Behavior
entity XOR is port ( A,B : in bit; Y : out bit); end XOR; architecture BEHAVIOR of XOR is begin Y <= (A and not B) or (not A and B); end BEHAVIOR;
Source: Mani Srivastava, UCLA

35. XOR in VHDL: Structure
architecture STRUCTURE of XOR is component NAND port ( A, B : in bit; Y : out bit); end component; signal C, D, E : bit; begin G1 : NAND port map (A, B, C); G2 : NAND port map (A => A, B => C, Y => D); G3 : NAND port map (C, B => B, Y => E); G4 : NAND port map (D, E, Y); end STRUCTURE;
Component Instantiation is just another Concurrent Statement!
Source: Mani Srivastava, UCLA

36. Source: Mani Srivastava, UCLA
XOR in VHDL: Mixed
architecture MIXED of XOR is component NAND port ( A, B : in bit; Y : out bit); end component; signal C, D, E : bit; begin D <= A nand C; E <= C nand B; G1 : NAND port map (A, B, C); G4 : NAND port map (D, E, Y); end MIXED;
Source: Mani Srivastava, UCLA

37. VHDL’s Model of a System
Static network of concurrent processes communicating using signals
A process has drivers for certain signals
A signal may be driven by multiple processes
Source: Mani Srivastava, UCLA

38. Anatomy of the VHDL Kernel
vhdl_simulator_kernel() { /* initialization phase */ time = 0 ns; for (each process P) { run P until it suspends;} while TRUE do { /* this is one simulation cycle ... */ if (no driver is active) { time = next time at which a driver is active or a process resumes; if (time = TIME’HIGH) break; } update_signals(); /* events may occur */ for (each process P) { if (P is sensitive to signal S & an event has occurred on S in this cycle) { resume P;     /* put it on a list ... */ } } for (each process P that has just resumed) { run P until it suspends;} } }
Source: Mani Srivastava, UCLA

39. Signals versus Variables
architecture DUMMY_1 of JUNK is signal Y : bit := ‘0’; begin process variable X : bit := ‘0’; begin wait for 10 ns; X := ‘1’; Y <= X; wait for 10 ns; -- What is Y at this point ? ‘1’ end process; end DUMMY_1;
architecture DUMMY_2 of JUNK is signal X, Y : bit := ‘0’; begin process begin wait for 10 ns; X <= ‘1’; Y <= X; wait for 10 ns; -- What is Y at this point ? ‘0’ end process; end DUMMY_2;
Signal assignments with 0 delay take effect only after a delta delay. i.e., in the next simulation cycle.
Source: Mani Srivastava, UCLA

40. Causality in VHDL The problem The remedy: Preemption consider a buffer
“output <= ‘1’ after 10 ns when input = ‘1’ else ‘0’ after 14ns;”
for a following input waveform
(0,1), (11,0), (19, 1), (20, 0), (21,1)
the output waveform is
(10,1), (25,0), (29, 1), (31,1), (34,0)
The remedy: Preemption
forward preemption: cancels events beyond the time the latest effectual event occurs
backward preemption: cancels events during the time the latest event is evaluated to the time its effectual event occurs
Transport delay = only forward preemption
Inertial delay = both forward and backward preemption

41. Projected waveform Preemptive timing Transport delay Inertial delay
Delay Models
VHDL has two distinct ways of modeling delays
Transport delay model
signal <= transport waveform;
for ideal devices with infinite frequency response in which every input pulse, however small, produces an output pulse
Inertial delay model
signal <= [reject time] inertial waveform;
for devices with “inertia” so that not all pulses go through
pulses < reject time are rejected
Projected waveform Preemptive timing Transport delay Inertial delay

42. Example: Transport Delay Model
Y <= 0 after 0 ns, 2 after 2 ns, 4 after 4 ns, 6 after 6 ns;
wait for 1 ns;
Y <= transport 3 after 2 ns, 5 after 4 ns, 7 after 6 ns;
Source: Mani Srivastava, UCLA

43. Example: Inertial Delay Model
Y <= 0 after 0 ns, 2 after 2 ns, 4 after 4 ns, 6 after 6 ns;
wait for 1 ns;
Y <= 3 after 2 ns, 5 after 4 ns, 7 after 6 ns;
Source: Mani Srivastava, UCLA

44. Signals with Multiple Drivers
Y <= A; -- in process1 and, Y <= B; -- in process2
What is the value of the signal in such a case?
VHDL uses the concept of a Resolution Function that is attached to a signal or a type, and is called every time the value of signal needs to be determined -- that is every time a driver changes value
Source: Mani Srivastava, UCLA

45. Resolution Function Example: Wire-And (open collector)
package RESOLVED is function wired_and (V:bit_vector) return bit; subtype rbit is wired_and bit; end RESOLVED; package body RESOLVED is function wired_and(V:bit_vector) return bit is begin for I in V’RANGE loop if V(I)= ‘0’ then return ‘0’; end if; end loop; return ‘1’; end wired_and; end RESOLVED;
Source: Mani Srivastava, UCLA

46. Guarded Signals: register & bus
Guarded signals are those whose drivers can be turned off
What happens when all drivers of a guarded signal are off?
Case 1:   retain the last driven value
signal X : bit register;
useful for modeling charge storage nodes
Case 2:    float to a user defined default value
signal Y : bit bus;
useful for modeling busses
Source: Mani Srivastava, UCLA

47. Guarded Signals (contd.)
Two ways to turn off the drivers
null waveform in sequential signal assignment
signal_name <= null after time_expression;
guarded concurrent signal assignment
block (data_bus_enable=’1’) begin data_bus <= guarded “0011”; end block;
Source: Mani Srivastava, UCLA

48. Source: Mani Srivastava, UCLA
Using VHDL Like C!
Normal sequential procedural programs can be written in VHDL without ever utilizing the event scheduler or the concurrent concepts.
Example:
entity HelloWorld is end; architecture C_LIKE of HelloWorld is use std.textio.all; begin main: process variable buf : line; begin write(buf, ”Hello World!”); writeln(output, buf); wait;   -- needed to terminate the program end process main; end C_LIKE;
Source: Mani Srivastava, UCLA

49. Language Features: Types
TYPE = Set of Values + Set of Operations
Typing in VHDL: SCALAR ENUMERATION e.g. character, bit, boolean NUMERIC: INTEGER, FLOATING PHYSICAL e.g. time COMPOSITE ARRAY e.g. bit_vector, string RECORD ACCESS FILE
Subtypes: constraints, resolution functions
IEEE standard 1164 logic system and 9-value logic

50. Scalar Types Numeric Types: Enumeration Physical integer, real
1.0, 10, 8#765#, 8#472#E+04, 2#10011#, 16#ab9#
ranges
type little_endian is range 0 to 31;
type big_endian is range 31downto 0;
Enumeration
identifier, character
type bit is (‘0’, ‘1’);
Physical
defines a postfix operator
type bit is (‘0’, ‘1’); type thor_bit is (‘U‘, ‘0’, ‘1’, ‘Z’); type memory_address is range 0 to 2**32-1; type small_float is range 0.0 to 1.0; type weight is range 0 to 1E8 units Gm; -- base unit Kg = 1000 Gm; -- kilogram Tonne = 1000 Kg; -- tonne end units;

51. Source: Mani Srivastava, UCLA
Array and Record Types
-- unconstrained array (defines an array type) type bit_vector is array (natural range <>) of bit; -- constrained array (define an array type and subtype) type word is array (0 to 31) of bit; -- another unconstrained array type memory is array (natural range <>) of word; -- following is illegal! type memory is array (natural range <>) of bit_vector; -- an example record type PERSON is record name : string(1 to 20); age : integer range 0 to 150; end record;
Source: Mani Srivastava, UCLA

52. SUBTYPE = TYPE + constraints or resolution function
Subtypes
SUBTYPE = TYPE + constraints or resolution function
Constraint can be on
index (subtype register is bit_vector (7 downto 0);)
range (subtype lowercase is character range ‘a’ to ‘z’;)
TYPE is the base-type of SUBTYPE
SUBTYPE inherits all the operators of TYPE
SUBTYPE can be more or less used interchangeably with TYPE
Examples:
subtype natural is integer range 0 to integer’HIGH; subtype good_thor_bit is thor_bit range ‘0’ to ‘1’; subtype small_float is real range 0.0 to 1.0;
Resolution function
type tstate is (‘0’, ‘1’, ‘z’);
type tvector is array (integer range <>) of tstate;
function resolve_tstate(X:tvector) return tstate;
subtype resolvedtristate is resolve_tstate tstate;

53. Predefined Attributes
For scalar type/subtype T
T’left, T’right, T’low, T’high
For any discrete or physical sub/type
T’pos(X) -- position number of X in T
T’val(N) -- value at position N of T
T’leftof(X)
T’rightof(X)
T’pred(X)
T’succ(X)
For an array A
A’left(N) -- left bound of Nth dimension of A
A’right(N)
A’low(N), A’high(N), A’range(N), A’reverse_range(N), A’length(N)
Ascending range: T’left = T’low, T’right = T’high
Descending range: T’left = T’high, T’right = T’low

54. Language Features: Overloading
Pre-defined operators (e.g., +, -, and, nand etc.) can be overloaded to call functions
Example:
function “and”(L,R : thor_bit) return thor_bit is begin if L=’0’ or R=’0’ then return ‘0’; elsif L=’1’ and R=’1’ then return ‘1’; else return ‘U’; end if; end “and”; now one can say C <= A and B; -- where A, B and C are of type thor_bit
Source: Mani Srivastava, UCLA

55. Source: Mani Srivastava, UCLA
Overloading (contd.)
Two subprograms (functions or procedures) can have the same name, i.e., the names can be overloaded. They are distinguished by parameter types. e.g.,
function MAX(A,B:integer) return integer;
function MAX(A,B:real) return real;
Source: Mani Srivastava, UCLA

56. Language Features: Configurations
Component declarations define a template for a design entity
The binding of an entity to this template is done through a configuration declaration
entity data_path is end data_path; architecture INCOMPLETE of data_path is component alu port(function : in alu_function; op1, op2 : in bit_vector_32; result : out bit_vector_32); end component; begin end INCOMPLETE;
Source: Mani Srivastava, UCLA

57. Configurations (contd.)…
configuration DEMO_CONFIG of data_path is for INCOMPLETE for all:alu use entity work.alu_cell(BEHAVIOR) port map (function_code => function, operand1 => op1, operand2 => op2, result => result, flags => open); end for; end for;
end DEMO_CONFIG;
Source: Mani Srivastava, UCLA

58. Language Features: Packages
A package is a collection of reusable declarations (constants, types, functions, procedures, signals etc.)
A package has a
declaration (interface), and a
body (contents) [optional]
Source: Mani Srivastava, UCLA

59. Source: Mani Srivastava, UCLA
Example of a Package
package SIMPLE_THOR is type thor_bit is (‘U’, ‘0’,’1’,’Z’); function “and”(L,R: thor_bit) return thor_bit; function “or”(L,R:thor_bit) return thor_bit; end SIMPLE_THOR; package body SIMPLE_THOR is function “and”(L,R: thor_bit) return thor_bit is begin end “and”; end SIMPLE_THOR; and then it can be used after saying library my_lib; use my_lib.SIMPLE_THOR.all;
Source: Mani Srivastava, UCLA

60. Language Features: Design Units and Libraries
VHDL constructs are written in a design file and the compiler puts them into a design library.
Libraries are made up of design units
primary design units
entity declarations
package declarations
configuration declarations
secondary design units
architecture bodies
package bodies
Source: Mani Srivastava, UCLA

61. Design Units and Libraries (contd.)
Libraries have a logical name and the OS maps the logical name to a physical name
for example, directories on UNIX
Two special libraries:
work:    the working design library
std:         contains packages standard and textio
To declare libraries that are referenced in a design unit:
library library_name;
To make certain library units directly visible:
use library_name.unit_name;
use also defines dependency among design units.
Source: Mani Srivastava, UCLA

62. Logic Simulation in VHDL
The 2-state bit data type is insufficient for low-level simulation
Multi-Valued types can easily be built in VHDL
several packages available
IEEE standard logic
Example: one may use a 4-value (‘U’,’0’,’1’,’Z’) system
but no notion of strength
only wired-X resolution
Source: Mani Srivastava, UCLA

63. The 9-value System Defined by IEEE 1164 Standard
Uninitialized, U
Forcing Unknown, X
Forcing 0, 0
Forcing 1, 1
High Impedance, Z
Weak Unknown, W
Weak 0, L
Weak 1, H
Don’t Care, -
Next Lecture: Simulation, Synthesis using VHDL