1. IEEE Floating Point Adder Verification
Using the IEEE Floating Point Standard for an add/subtract execution units
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

2. Copyright 2006 - Joanne DeGroat, ECE, OSU
Lecture overview
The Interface
Part by part
A floating point adder design
Verifying the design
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

3. The floating point standard
Single Precision
Value of bits stored in representation is:
If e=255 and f /= 0, then v is NaN regardless of s
If e=255 and f = 0, then v = (-1)s ¥
If 0 < e < 255, then v = (-1)s 2e-127 (1.f) – normalized number
If e = 0 and f /= 0, the v = (-1)s (0.f)
Denormalized numbers – allow for graceful underflow
If e = 0 and f = 0 the v = (-1)s 0 (zero)
1/8/ L24 IEEE Floating Point Basics
Copyright Joanne DeGroat, ECE, OSU

4. The partitioning of the design
From adjusting the inputs to prepare to add
To add
To renormalize
To round
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

5. Copyright 2006 - Joanne DeGroat, ECE, OSU
The first section
Prepare to add
Identify type of inputs and appropriately adjust operands
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

6. The exponent unit portion
Must get the larger exponent
And the difference between the exponents which is the shift distance
Also several control signals
Exponent all 0s and all 1s
Exponent A>B, A<B, =
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

7. Code for this section - behavioral
Most of code is generation of various signals and movement of data in muxes
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

8. Copyright 2006 - Joanne DeGroat, ECE, OSU
Renormalization Unit
Have exponent and mantissa to deal with.
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

9. Copyright 2006 - Joanne DeGroat, ECE, OSU
Don’t forget the flags
Any arithmetic unit output flags on the status and validity of the result.
The flags to be generated are output from various control signals or combinations of various control signals.
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

10. To test (verify) the design
Must test for normal operation and boundary conditions
Will check A by B
NaN NaN
+/- infinity /- infinity
+/ /- 0
Denorm Denorm
Norm Norm
For both direct and all crossed pairings
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

11. Copyright 2006 - Joanne DeGroat, ECE, OSU
Boundary conditions
Wish to check several boundary conditions
Denorm + Denorm = Max Denorm
Denorm + Denorm = Min Norm
Norm – Norm = Max Denorm …
Rounding using first guard bit
Rounding using 1st and 2nd guard bits
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

12. Copyright 2006 - Joanne DeGroat, ECE, OSU
Testing
Testing of the design code is not necessarily the same as the testing the would be done on the chip.
The “testing” of the design is call verification and must insure that all possible input combinations produce the specified output.
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

13. Scan of entire architecture
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

14. Copyright 2006 - Joanne DeGroat, ECE, OSU
Scan of the chip
1/8/ L25 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

15. So what goes into the test plan
Test plan lays out what is to be verified
Test plan outlines the test application methodology to be used.
Outlines how the testbench will get the tests and apply them to the unit.
Outlines how the results will be checked – this unit has complexity levels that visual check is not adequate.
Test plan also details the vector test set to be applied. Provides rational as the level of functional coverage that this test set will provide.
Clearly defines what is “success”. So you know when you are done!!
1/8/ L2 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU

16. And then a final verification report
Details of implementation of the verification plan.
What vectors were applied.
Test that failed
Detail of issues in the DUT that require fixing
Details on how the test vectors were generated.
Many be in programs other than HDL.
1/8/ L2 Floating Point Adder
Copyright Joanne DeGroat, ECE, OSU