Presentation is loading. Please wait.

Presentation is loading. Please wait.

EE694v-Verification-Lect6-1- Lecture 6 - Writing Tests A difference if treating the design as a black box or if you have access to internal signals EE762.

Published byZoie Dougherty Modified over 9 years ago

Similar presentations

Presentation on theme: "EE694v-Verification-Lect6-1- Lecture 6 - Writing Tests A difference if treating the design as a black box or if you have access to internal signals EE762."— Presentation transcript:

1 EE694v-Verification-Lect6-1- Lecture 6 - Writing Tests A difference if treating the design as a black box or if you have access to internal signals EE762 assignment testbenches treat student design as a black box Must know what you are testing Must test corner cases

2 EE694v-Verification-Lect6-2- Floating Point Multiplier Used as a EE762 assignment Project Assignment #10Floating Pt UnitDUE: Mon Mar 10 In this assignment you will use VHDL to describe the function of a floating point multiplier. The multiplier will accept IEEE Standard 754 single precision inputs and produce single precision output. It will support NaN, ±∞, ±0, normalized numbers, and denormalized numbers. The interface to the design will be:

3 EE694v-Verification-Lect6-3- The Assignment Inputs will arrive as per the attached specification and test bench. Your design will latch inputs using the latch input signal. Your design will drive the outputs using the drive signal. After driving the output, when the drive signal again goes high, you must drive the bus back to high impedance. Use the component interface given in the testbench STEP 1) Write the initial architecture. In the initial architecture, simply latch the input, route the A input to the output, and correctly drive the C bus. If you get this step working correctly the rest will go much easier. SIMULATE STEP 2) Write a VHDL process to do the floating point multiply. Recommendation : As you start to write your routine handle special cases first. Write the code to handle the NaNs - then simulate and check that you handle the NaNs correctly. Note that ±∞ * ±0 results in a NaN.. Then correctly handle ±∞, and verify through simulation. Then correctly handle ±0 and simulate. Finally do the cases where you actually have to multiply. You can use process(es), concurrent signal assignment, etc., as you would like. You will find the following files in ~degroat/ee762_assign fpmtb.vhdl - the test bench - the component declaration, configuration,and instantiation have been done but you can change them if you want to. fpmvectors - a list of the input stimul

4 EE694v-Verification-Lect6-4- The Assignment (2) fpm.do - do file for listing and waveform Other NOTES for floating point multiplier. The test bench also uses a concurrent procedure call that reads the testvector file in ~degroat/ee762_assign/fpmvectors. Use of these vectors is hard coded in the concurrent procedure as are the checks and grading routine. This procedure has been compiled and is in the library assign in this directory. To provide the mapping to it you must execute the unix command qhmap assign /user2/faculty/degroat/ee762_assign/assign This provides the logical mapping such that the library clause in the test bench know where library assign is located. This must be done prior to compiling the test bench. The procedure will also do the grading of this assignment.

5 EE694v-Verification-Lect6-5- Floating Point Standard Single Precision Floating Point Format Value is If e = 255 and f ≠ 0, then v is NaN regardless of s If e = 255 and f = 0, then v = (-1)s ∞ If 0 < e < 255, then v = (-1)s 2e- 127 (1.f) If e = 0 and f ≠ 0, then v = (-1)s 2- 126 (x.f) (denormalized numbers)(x is msb of value stored) If e = 0 and f = 0, then v = (-1)s 0 (zero)

6 EE694v-Verification-Lect6-6- Other Specifications Inputs are in IEEE 754 Single Precision Results are in IEEE 754 Single Precision Format Unit can latch A and B inputs from parallel busses Must be able to handle both numerical values and special cases –NaNs, ±inif, –±zero, –±normalized numbers, ±denormalized numbers

7 EE694v-Verification-Lect6-7- What to Check How to test the floating point multiplier for both timing of inputs and outputs and functional operation? Assume you have no knowledge of how design is going to be implemented

8 EE694v-Verification-Lect6-8- The Test Vectors Must test for normal operation and boundary conditions A inputbyB inputNaN±∞±0±Denorm±Norm Denorm * OtherVal = Max Denorm Denorm * OtherVal = Min Norm Rounding using first guard bit Rounding using 1st and 2nd guart bits

9 EE694v-Verification-Lect6-9- The Inputs – Example 1...NaN 01111111100000000000000000000001...NaN 01111111100000000000000000000001...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001.+INIF 01111111100000000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001.-INIF 11111111100000000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001....+0 00000000000000000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001....-0 10000000000000000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001....+1 00111111100000000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001....-1 10111111100000000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001...+25 01000001110010000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001...-25 11000001110010000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001..+100 01000010110010000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001.1/100 00111100001000111101011100001010...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001+DNORM 00000000001010000000000000000000...Nan 01111111100000000000000000000001...NaN 01111111100000000000000000000001-DNORM 10000000001010000000000000000000...Nan 01111111100000000000000000000001.+INIF 01111111100000000000000000000000...NaN 01111111100000000000000000000001...NaN 01111111100000000000000000000001

10 EE694v-Verification-Lect6-10- The Inputs – Example 2...+25 01000001110010000000000000000000....+0 00000000000000000000000000000000....+0 00000000000000000000000000000000...+25 01000001110010000000000000000000....-0 10000000000000000000000000000000....-0 10000000000000000000000000000000...+25 01000001110010000000000000000000....+1 00111111100000000000000000000000...+25 01000001110010000000000000000000...+25 01000001110010000000000000000000....-1 10111111100000000000000000000000...-25 11000001110010000000000000000000...+25 01000001110010000000000000000000...+25 01000001110010000000000000000000..+625 01000100000111000100000000000000...+25 01000001110010000000000000000000...-25 11000001110010000000000000000000..-625 11000100000111000100000000000000...+25 01000001110010000000000000000000..+100 01000010110010000000000000000000.+2500 01000101000111000100000000000000...+25 01000001110010000000000000000000.1/100 00111100001000111101011100001010.+0.25 00111110011111111111111111111111...+25 01000001110010000000000000000000+DNORM 00000000001010000000000000000000 small1 00000001111110100000000000000000...+25 01000001110010000000000000000000-DNORM 10000000001010000000000000000000 small2 10000001111110100000000000000000...-25 11000001110010000000000000000000...NaN 01111111100000000000000000000001...NaN 01111111100000000000000000000001...-25 11000001110010000000000000000000.+INIF 01111111100000000000000000000000.-INIF 11111111100000000000000000000000...-25 11000001110010000000000000000000.-INIF 11111111100000000000000000000000.+INIF 01111111100000000000000000000000...-25 11000001110010000000000000000000....+0 00000000000000000000000000000000....-0 10000000000000000000000000000000

11 EE694v-Verification-Lect6-11- Applying Inputs to Design Inputs are read from a file and applied to the design WHILE (NOT ENDFILE(test_data)) LOOP --get next input test vector and expected result readline(test_data,cur_line); read(cur_line,aid); read(cur_line,a_test_val); read(cur_line,bid); read(cur_line,b_test_val); readline(test_data,cur_line); read(cur_line,resid);read(cur_line,result_val); std_result_val := To_StdLogicVector(result_val); num_tests := num_tests + 1; -- run through bus cycle to send data to unit aid_sig <= "======", aid after 20 ns; bid_sig <= "======", bid after 20 ns; resid_sig <= "======", resid after 20 ns; -- drive signals on bus aval <= To_StdLogicVector(a_test_val) after 20 ns, HIGHZ after 80 ns; bval <= To_StdLogicVector(b_test_val) after 20 ns, HIGHZ after 80 ns; latch <= '0' after 20 ns, '1' after 70 ns; wait for 100 ns; drive <= '0' after 20 ns, '1' after 80 ns; exp_res <= std_result_val after 20 ns, HIGHZ after 80 ns; wait for 50 ns; ASSERT (C = std_result_val) REPORT "result does not agree with expected result" SEVERITY WARNING; IF (C /= std_result_val) THEN num_errors := num_errors + 1; err_sig <= '1', '0' after 10 ns; END IF; wait for 50 ns; END LOOP;

12 EE694v-Verification-Lect6-12- The File I/O Declarations First must set up the basic declarations

13 EE694v-Verification-Lect6-13- File I/O And then must also do the declarations for File I/O Note that the file I/O here uses the 1987 version of the language

14 EE694v-Verification-Lect6-14- Checking Results Timing is checked when result is expected on bus and again just prior to bus going back to high impedance. Busses are also checked that they go back to a value of high impedance When results do not match what is expected a signal called error goes to ‘1’ for 10 ns

Download ppt "EE694v-Verification-Lect6-1- Lecture 6 - Writing Tests A difference if treating the design as a black box or if you have access to internal signals EE762."

Similar presentations

Computer Architecture

Computer Architecture
VHDL in digital circuit synthesis (tutorial) dr inż. Miron Kłosowski EA 309

VHDL in digital circuit synthesis (tutorial) dr inż. Miron Kłosowski EA 309
1 Software Engineering Lecture 11 Software Testing.

1 Software Engineering Lecture 11 Software Testing.
L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit.

L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit.
Lab Lecture 3 VHDL Architecture styles and Test Bench -Aahlad.

Lab Lecture 3 VHDL Architecture styles and Test Bench -Aahlad.
Chapter 5: Computer Systems Organization Invitation to Computer Science, Java Version, Third Edition.

Chapter 5: Computer Systems Organization Invitation to Computer Science, Java Version, Third Edition.
Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 2 Microcomputer Systems Design (Embedded Systems)

Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 2 Microcomputer Systems Design (Embedded Systems)
VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.

VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.
Topics Entity DeclarationsEntity Declarations Port ClausePort Clause Component DeclarationComponent Declaration Configuration DeclarationConfiguration.

Topics Entity DeclarationsEntity Declarations Port ClausePort Clause Component DeclarationComponent Declaration Configuration DeclarationConfiguration.
EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,

EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,
Simple Testbenches Behavioral Modeling of Combinational Logic

Simple Testbenches Behavioral Modeling of Combinational Logic
1/8/2007 - L24 IEEE Floating Point Basics Copyright 2006 - Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.

1/8/ L24 IEEE Floating Point Basics Copyright Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.
Introduction to VHDL (part 2)

Introduction to VHDL (part 2)
Advanced FPGA Based System Design Lecture-9 & 10 VHDL Sequential Code By: Dr Imtiaz Hussain 1.

Advanced FPGA Based System Design Lecture-9 & 10 VHDL Sequential Code By: Dr Imtiaz Hussain 1.
ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.

ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.
Understanding the CORBA Model. What is CORBA?  The Common Object Request Broker Architecture (CORBA) allows distributed applications to interoperate.

Understanding the CORBA Model. What is CORBA?  The Common Object Request Broker Architecture (CORBA) allows distributed applications to interoperate.
IAY 0600 Digitaalsüsteemide disain Event-Driven Simulation Alexander Sudnitson Tallinn University of Technology.

IAY 0600 Digitaalsüsteemide disain Event-Driven Simulation Alexander Sudnitson Tallinn University of Technology.
ECE 545 Project 1 Part IV Key Scheduling Final Integration List of Deliverables.

ECE 545 Project 1 Part IV Key Scheduling Final Integration List of Deliverables.
1/8/2007 - L24 IEEE Floating Point Basics Copyright 2006 - Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.

1/8/ L24 IEEE Floating Point Basics Copyright Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.
Graduate Computer Architecture I VHDL Structure and Testing Michael Sorensen.

Graduate Computer Architecture I VHDL Structure and Testing Michael Sorensen.

Similar presentations

Ads by Google