1. New Challenges in IC Design … with a focus on variability …
SBCCI 2004 Panel Discussion
Chandu Visweswariah Research Staff Member
IBM Thomas J. Watson Research Center
Yorktown Heights, NY
I would like to thank the organizers for inviting me to this beautiful part of Brazil to participate in this conference.
My presentation will be focusing on variability as the main driver of present and future paradigm shifts in IC design.
IBM makes both ASICs and processors, and is in fact #1 world-wide in ASICs. I myself work on both ASICs and processors, but for the purposes of this presentation I will wear my ASIC hat.
© Chandu Visweswariah, 2004
New Challenges in IC Design

2. Where will performance come from?
Technology scaling
will require ever-more exotic materials and tricks
will yield diminishing performance enhancements
Performance will come from
multiple processors/cores
packaging options (3D ICs, silicon carrier)
better memory hierarchies
better tools
better compilers
© Chandu Visweswariah, 2004
New Challenges in IC Design

3. New Challenges in IC Design
Outline
Challenge #1: migrate from corner-based timing to statistical timing
Challenge #2: adopt robust design methodologies and practices
Challenge #3: simultaneous timing and (leakage) power sign-off
Challenge #4: stop targeting worst-case design; rather, design adaptive circuits that can recover from low-probability problems
This is just an outline… get through this slide quickly.
© Chandu Visweswariah, 2004
New Challenges in IC Design

4. The march of technology
Performance
Is this worth a huge investment?
Moore’s Law promises exponential performance gains; however, the gains are tapering off and it requires ever-more exotic tricks and new materials to stay on the curve. What is worse, variability is proportionately increasing. Critical dimensions are scaling faster than we can control them; the number of significant sources of variation is increasing. The ASIC industry typically follows the bottom of the error bars. Depending on how this diagram is drawn, we may not even get any performance gain going from 90 nm to 65 nm. The way to get around this is:
Do not go to 3-sigma individually in every dimension; rather, target the true 3-sigma of the process;
Build robust circuits so that even if the process shows variation, the circuit performance is not impacted to first order.
Technology generation
© Chandu Visweswariah, 2004
New Challenges in IC Design

5. 1: Corner-based vs. statistical timing
Challenge #1: go from corner-based timing to statistical timing. This is a picture of the process space. The shading shows roughly the likelihood of chips falling at a particular point in the process space. If delay is separable and monotonic in each source of variation, the timing can be BOUNDED by checking all (exponential number of) corners.
© Chandu Visweswariah, 2004
New Challenges in IC Design

6. Benefit of statistical timing
n = # independent sources of variation (say 9)
 = total variability in critical path delay (say 5%)
Fractional increase in frequency with a 3 sign-off instead of 3n sign-off
Assumes sources of variation are roughly equally significant
Let us try to quantify the benefits of statistical timing over corner-based timing. In the case of corner-based sign-off, delay = D(1+3n). In the case of statistical sign-off, delay=D(1+3). Difference in delay = D3(n-1). Hence percentage benefit in frequency = the formula shown. We can plot this formula with a simple spread sheet to suit your assumptions.
© Chandu Visweswariah, 2004
New Challenges in IC Design

7. Corner-based vs. statistical
With 7 sources of variation and 5% variability, there is a frequency difference of over 20%. With 9 sources, that becomes 26%, as we calculated in the previous slide.
© Chandu Visweswariah, 2004
New Challenges in IC Design

8. New Challenges in IC Design
2: Robustness
Reduce sensitivity of performance to variations; examples:
N/P mistracking: avoid too many tall N or tall P stacks in critical paths
Gate/wire mistracking: use equal fractions of gates and wires in data and clock paths
ACLV/OCV: use compact layouts so that capturing and launching paths are close by
Vt mistracking: use equal fractions of low Vt transistors in critical data and clock paths
The next main challenge is to target robust design. The timing of all digital circuits is controlled by data and clock signals racing against each other. Go through examples.
© Chandu Visweswariah, 2004
New Challenges in IC Design

9. New Challenges in IC Design
Q&A
Q: Where will the models come from?
A: IDMs have an advantage
Q: What will the models look like?
A: Analytic forms are more conducive than table-based delay modeling formats
Q: Can timers handle the capacity?
A: Yes; 2.1M gate design timed in 69 minutes with 10.9 GB memory; 1.1M gate design timed in 110 minutes (dominated by load time) with 4.3 GB memory
Q: How will it be phased in?
A: (a) true 3 sign-off (b) implicit robustness credit (c) explicit robustness targeting (d) at-speed test for yield/speed tradeoffs
IDMs = Integrated Device Manufacturers
On question 2: tweak Synopsys
On question 3: some of our own results
On question 4: explain the difference between implicit and explicit robustness credit; further, at-speed test will allow exploitation of tradeoffs
© Chandu Visweswariah, 2004
New Challenges in IC Design

10. BEOL early-mode variability on ASIC part
Exhaustive corner analysis: -225 ps
-3 slack: -162 ps
Pessimism
reduction
This chart shows actual timing numbers from a real ASIC part that had early mode timing problems due to metal mistracking. The cones of logic represented by all end-points whose slack was between -225 ps and -162 ps are all cones that would be needlessly optimized were we to use corner-based timing.
*Early mode; variability in 7 metal levels
© Chandu Visweswariah, 2004
New Challenges in IC Design

11. 3: Simultaneous power/timing sign-off
Probability
Good
chips
Too
slow
Too
leaky
Performance and leakage power are intimately tied! If we can compute both in some canonical form so that the correlation between them is captured, then we can employ simultaneous power/timing sign-off. Vt
© Chandu Visweswariah, 2004
New Challenges in IC Design

12. New Challenges in IC Design
4: Adaptive circuits
Key idea: we are penalizing performance by covering low-probability problems
Instead, recover from the low-probability problems adaptively
sensor circuits: to sense temperature, a late signal, a wrong logical value, Vt, a mistracking situation
actuator circuits: to change back-gate bias, change Vdd, repeat a computation, gate the clock, throttle instruction issue
Adaptive circuits protect against static variability, dynamic variability and single-event upsets
A wealth of design, CAD, methodology and verification problems suggest themselves!
Finally, we can take a card from the communications circuits community where almost no circuit works perfectly, but the system still functions correctly. Example: RAZOR work from U Michigan. Many nice research problems are available in this domain!
© Chandu Visweswariah, 2004
New Challenges in IC Design

13. New Challenges in IC Design
Conclusion
Variability is causing a number of problems
leakage power
timing closure
excessive pessimism
worst-case design kills scaling benefit
Paradigm shifts are periods of opportunity: One person’s headache is another’s windfall!
Paradigm shifts are periods of opportunity!
© Chandu Visweswariah, 2004
New Challenges in IC Design