© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities1 of 80 Statistical Analysis and Design: From Picoseconds.

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities1 of 80 Statistical Analysis and Design: From Picoseconds to Probabilities Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY http://www.research.ibm.com/people/c/chandu With acknowledgments to the extended timing, modeling, synthesis and methodology teams at IBM Yorktown, Fishkill and Burlington

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities3 of 80 Propositions (and outline) 1.Variability is proportionately increasing; therefore, a new paradigm is required 2.Correlations matter 3.Statistical timing tools are rising to the challenge 4.Robustness is an important metric 5.Statistical treatment of variability will pervade all aspects of chip design methodology, manufacturing and test ASICs and processors will both benefit

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities6 of 80 The source of the problem Variability is proportionately increasing –manufacturing FEOL: critical dimensions are scaling faster than our control of them BEOL: variability dramatically increases the number of independent and significant sources of variation –environmental (V dd, temperature) –fatigue (NBTI, hot electron effect) –across-chip (OCV/ACLV, temperature, V dd ) –circuit design (PLL jitter, coupling noise, SOI history) –model-to-hardware correlation

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities7 of 80 Delay impact of variations ParameterDelay Impact BEOL metal (Metal mistrack, thin/thick wires) -10% → +25% Environmental (Voltage islands, IR drop, temperature)  15 % Device fatigue (NBTI, hot electron effects)  10% V t and T ox device family tracking (Can have multiple V t and T ox device families)  5% Model/hardware uncertainty (Per cell type)  5% N/P mistrack (Fast rise/slow fall, fast fall/slow rise)  10% PLL (Jitter, duty cycle, phase error)  10% [Courtesy Kerim Kalafala] Requires 2 20 timing runs or [-65%,+80%] guard band!

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities8 of 80 Can you answer these questions about your favorite digital chip? What does 5% random delay variability on each gate and wire do to your frequency distribution? What does 5% correlated delay variability do to your frequency distribution? What % delay variation leads to a hold violation? How many yield points does OCV/ACLV cost? What is the shape of your parametric yield curve? What is the sensitivity of your chip’s frequency to –thickness of a metal level? –gate/wire mistracking? –N/P mistracking? –mistracking between metal levels i and j?

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities9 of 80 New paradigm required ASICs –old paradigm: sign-off is corner- or case-based –would require 2 20 timing runs to hit all corners –cumbersome, risky and pessimistic all at the same time! Microprocessors –for the most part, nominal performance is targeted –some ad hoc methods to deal with certain types of mistracking Both –our design/synthesis methods do not target robustness, nor do our timing tools measure robustness or give credit for robust design Solution: statistical timing and optimization

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities14 of 80 What is a statistical timer? Static timer Delay and slew models Netlist + assertions 1. Slack 2. Diagnostics Statistics of the sources of variability Dependence on sources of variability 1. Yield curve 2. Diagnostics Statistical timer

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities17 of 80 Importance of correlations Consider a circuit with 50K latches, each with a setup and hold test, each of which has a 99.99% probability of being met If all tests are perfectly correlated, yield = 99.99% If all tests are perfectly independent, yield = 0.005% The truth is closer to the perfectly correlated case!

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities24 of 80 Types of variability Global within a die/reticle –metal dimensions –device family strength mistracking –ambient temperature and power supply Spatial/local correlation across a die/reticle –L eff –junction temperature, V dd Independently random –t ox –doping effects

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities25 of 80 First-cut approach to static timing a b c + + MAX b a c + + Deterministic Statistical Question: what do correlations do to the MAX and PLUS operations?

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities36 of 80 Conventional wisdom revisited Conventional wisdom says, “Use sizing and multiple V t s to tune the circuit aggressively, creating a wall of critical paths –the new wisdom is to optimize the expected value of the critical path delay, which in turn means reducing the wall of critical paths Conventional wisdom says, “Make pipeline stages short and crank up clock frequency” –the new wisdom is to take advantage of RMS/ RSS effects in moderately longer pipelines

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities37 of 80 Separating out independent randomness Old: N(20,1) New: systematic variability N(20,2/3) New: independent variability N(0,1/3)

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities38 of 80 Case study Consider a critical path of 50 identical gates Old: assume delay of each gate is N(20,1) ps (corner delays are 17 and 23 ps) New: assume delay of each gate is N(20,2/3) ps + N(0,1/3) ps (same corner delays) Old: critical path delay (3  ) = 23  50 = 1150 ps New: critical path delay (3  ) = 22  50 + 3  1/3  50 = 1100 + 7.1 = 1107.1 Improvement in critical path delay = 3.7% This case study can be generalized

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities39 of 80 Generalization of case study As N↑, the benefit ↑ As v↑, the benefit ↑ As f↑, the benefit ↑ Rule of thumb: for 50 stages and 5% variability (  ), each percent of independent variability buys 0.1% of critical path delay improvement

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities42 of 80 M equally critical paths Basic issue –suppose there are M equally critical paths –each of these paths has already received RMS credit, so the delay of each path consists of a constant which is the nominal/intrinsic delay of the path plus the corner-based systematic variability an independent variability part for which we have received an RMS credit, so there is a small probability that the delay is beyond the 3  limit –with a large number of equally critical paths, the 3  of the MAX delay of all M paths is not equal to the 3  delay of each of the M paths –question: how big is this sigma shift?

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities43 of 80 A little analysis Example: with M=50, we have to use a 4.037  value on the random part instead of 3  to get a “true 3  ” delay on the maximum delay of 50 paths; this diminishes RSS credit The benefit after taking this into account is plotted in general versus M and N on the next page, assuming f=1/3, v=5%

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities45 of 80 Statistical timing experiment N(10,1) Data Clock Latch with zero setup guard time How will slack change with  ? N(10,1) Arrival time=0

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities47 of 80 There’s no question: correlation’s a pain Of neat math. formulas, it’s the bain! Though your timer becomes a morass It’s correlation that saves your … (chip)

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities49 of 80 Statistical timing tools Path-based –conduct a nominal timing analysis –list a representative set of critical paths (question: how may paths? question: which paths?) –model the delay/slack of each path as a function of random variables (the underlying sources of variation) –predict the parametric yield curve (statistical MIN of all path slacks), as well as generate diagnostics Block-based –propagate arrival times and required arrival times in the form of probability distributions –linear time –approximate, quick-and-dirty

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities51 of 80 Feasible region Feasible region in parameter-space Integration of the JPDF over the feasible region is the parametric yield Yield improvement or line-tailoring vector JPDF of global parameters

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities54 of 80 Canonical variational delay model Correlations are the problem –in a circuit with 1M nodes and 2M edges and 12 timing values per node/edge, we DO NOT want to store or manipulate a 36M x 36M covariance matrix! –instead, parameterize all timing quantities by the sources of variation –first-order canonical model: Constant (nominal value) Random uncertainty (deviation from nominal value) Sensitivities Deviation of global sources of variation from their nominal values

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities55 of 80 Procedure Express all delays, slews, arrival times, required arrival times and slacks in canonical form Propagate arrival times forward through the timing graph while preserving correlations Propagate required arrival times backward while preserving correlations Slack is the difference of arrival and required arrival times Each path, node and edge has a probability of being critical; these criticality probabilities can be computed easily All results are also available in canonical form; these diagnostics are extremely useful!

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities56 of 80 Interpreting statistical timing results Critical path is not unique Critical paths can be listed in order of probability of being critical –this should be the order in which the timing of paths is “fixed” or optimized In deterministic timing, slack is identical along the critical path This property does not hold in the case of statistical timing Slacks reflect not only timing shortfalls, but also robustness shortfalls

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities58 of 80 Sample comparison to Monte Carlo Monte Carlo, 14 hours CPU time Block-based statistical timer, 18 seconds CPU time Test chip (3K gates)

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities59 of 80 Overhead of statistical calculations Run time overhead –about 20% on batch operation –about 50% on the actual arrival time propagation Memory overhead –about 100% depending on the number of sources of variation and complexity of the models Capacity –able to time 2M+ gate ASIC chips on 64-bit machines

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities60 of 80 Methods of handling ACLV/OCV ACLV/OCV is traditionally handled by heuristic derating coefficients –an early/late delay split is applied, and late data is compared to early clock and vice versa However, we want to give credit to compactly laid out launching/capturing path pairs and penalize path pairs that snake all over the chip By taking advantage of spatial correlation, we can obtain proximity credit

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities61 of 80 Path-based solution The setup and hold test can be penalized by an early/late split based on the size of this bounding box

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities64 of 80 Section 4: Robust Design … sure, the process is all over the place, but can I use design techniques to attenuate the effect?

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities65 of 80 Remember these? In addition to correctness, power, signal integrity and area, please welcome robustness to variation as a first-class design metric

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities66 of 80 Robust design Tremendously valuable if the statistical timer produces timing results in 1 st order canonical form: First order model Constant (nominal part) Sensitivities Global variations Random uncertainty

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities67 of 80 Opportunities for robust design Find out which sources of variation are the biggest yield detractors; quantify robustness of a design Any commonality between data and clock cancels out to first order –voltage islands, gate types, device types, metal levels used for interconnect, proximity of launching and capturing paths Robustness-enhancing design decisions –high sensitivity to N/P mistrack  resynthesize with fewer tall P stacks, for example –high sensitivity to a particular metal level  re-route –high sensitivity to Vt mistrack  try to balance use of low/high Vt devices in capturing and launching paths –high sensitivity to wire/gate mistrack  try to rebalance delay Producing timing results in canonical form can help with line tailoring

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities68 of 80 How synthesis techniques will evolve Phase 1 –true 3  timing sign-off with statistical timing Phase 2 –use statistical timing to guide the physical synthesis and routing optimization (implicit robustness credit) Phase 3 –further reduce performance  by actively targeting robustness (explicit robustness credit) Phase 4 –with the mainstream availability of at-speed test, enable yield/performance tradeoffs

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities71 of 80 800 MHz 11 22 33 -3  -2  -1  -2  -3  33 22 11 1 GHz 900 MHz FEOL BEOL Check front-end corners: possible escapes

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities72 of 80 600 MHz 800 MHz 11 22 33 -3  -2  -1  -2  -3  33 22 11 1 GHz 900 MHz FEOL BEOL Check all corners: no escapes, pessimistic

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities73 of 80 600 MHz 700 MHz 800 MHz 11 22 33 -3  -2  -1  -2  -3  33 22 11 1 GHz 900 MHz FEOL BEOL Statistical timing: no escapes, less pessimism

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities74 of 80 ASIC timing methodology Checking “all corners” is very pessimistic Checking “all corners” is intractable Statistical timing fits in “naturally” With the same area/power targets and the same tool suite, but a statistical timer to guide the placement, routing and optimization, the estimated performance improvement is of the order of 20% in 90nm technology Test coverage can be improved by exploiting statistical timing results With at-speed test, arbitrary performance vs. yield tradeoffs can be made based on business needs

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities75 of 80 Good chips Path report file with criticality probabilities + process coverage Canonical variational delay model Statistical timing Technology characterization + delay model generation Test vector generation At-speed test Bad chips with failing path signatures Path sensitivities Correlation analysis and diagnosis Model-to-hardware correlation and/or line tailoring MHC, line tailoring

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities76 of 80 Possible microprocessor methodology Individual macros Robustness budgetAssertions Statistical timing for optimization “Sign-off” statistical timing and abstraction Global wires Other macros Unit or chip-level statistical timing for optimization Unit or chip-level statistical “sign-off” timing (Mostly) FEOL variability models (Mostly) BEOL variability models Update timing and robustness budgets

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities77 of 80 Good chips Too slow Too leaky Vt variations Requires simultaneous power/timing sign-off Probability Vt

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities79 of 80 Propositions 1.Variability is proportionately increasing; therefore, a new paradigm is required 2.Correlations matter 3.Statistical timing tools are rising to the challenge 4.Robustness is an important metric 5.Statistical treatment of variability will pervade all aspects of chip design and manufacturing ASICs and processors will both benefit

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities80 of 80 Quotable quotes* Statistical thinking will one day be as necessary for efficient (chip-design) citizenship as the ability to read and write. -- H. G. Wells There are three kinds of lies: lies, damned lies and statistics. -- Disraeli It ain’t so much the things we don’t know that get us in trouble. It’s the things we know that ain’t so. -- Artemus Ward Round numbers are always false. -- Samuel Johnson *From “How to Lie with Statistics,” by Darrell Huff, Norton, 1954

© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities1 of 80 Statistical Analysis and Design: From Picoseconds.

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© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities1 of 80 Statistical Analysis and Design: From Picoseconds.

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Presentation on theme: "© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities1 of 80 Statistical Analysis and Design: From Picoseconds."— Presentation transcript:

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