1. EE 5340 Semiconductor Device Theory Lecture 23 - Fall 2003
Professor Ronald L. Carter
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2. Ideal 2-terminal MOS capacitor/diode
conducting gate,
area = LW
Vgate
-xox
SiO2 y L
silicon substrate
tsub
Vsub x
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3. Band models (approx. scale)
metal
silicon dioxide
p-type s/c Eo
qcox
~ 0.95 eV Eo Eo
qcSi= 4.05eV
qfm= 4.1 eV for Al Ec
qfs,p
Eg,ox
~ 8 eV
EFm Ec
EFp
EFi Ev Ev
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4. Flat band condition (approx. scale)
SiO2
p-Si
q(fm-cox)= 3.15 eV
q(cox-cSi)=3.1eV
Ec,Ox
qffp= 3.95eV
EFm Ec
Eg,ox~8eV
EFi
EFp Ev Ev
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5. MOS surface states** p- substr = n-channel
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6. n-substr accumulation (p-channel)
Fig 10.7a*
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7. n-substrate depletion (p-channel)
Fig 10.7b*
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8. n-substrate inversion (p-channel)
Fig 10.7*
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9. Values for gate work function, fm
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10. Values for fms with metal gate
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11. Values for fms with silicon gate
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12. Typical fms values
Fig 10.15*
fms
(V)
NB (cm-3)
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13. Flat band with oxide charge (approx. scale)
SiO2
p-Si
+<--Vox-->-
q(Vox)
Ec,Ox
q(ffp-cox)
q(fm-cox) Ex
Eg,ox~8eV
EFm Ec
EFi
EFp
q(VFB) Ev
VFB= VG-VB, when Si bands are flat Ev
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14. Flat-band parameters for n-channel (p-subst)
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15. Flat-band parameters for p-channel (n-subst)
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16. Inversion for p-Si Vgate>VTh>VFB
Vgate> VFB
EOx,x> 0
e- e- e- e- e-
Depl Reg
Acceptors
Vsub = 0
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17. Approximation concept “Onset of Strong Inv”
OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh
Assume ns = 0 for VG < VTh
Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh
Cd,min = eSi/xd,max for VG > VTh
Assume ns > 0 for VG > VTh
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18. MOS Bands at OSI p-substr = n-channel
Fig 10.9*
2q|fp|
qfp
xd,max
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19. Computing the D.R. W and Q at O.S.I.Ex
Emax x
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20. Calculation of the threshold cond, VT
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21. Equations for VT calculation
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22. Fully biased n-MOS capacitorVG
Channel if VG > VT VS VD
EOx,x> 0 n+
e- e- e- e- e- e- n+
p-substrate
Vsub=VB
Depl Reg
Acceptors y L
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23. MOS energy bands at Si surface for n-channel
Fig 8.10**
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24. Computing the D.R. W and Q at O.S.I.Ex
Emax x
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25. Q’d,max and xd,max for biased MOS capacitor
Fig 8.11**
xd,max
(mm)
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26. Fully biased n- channel VT calc
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27. n-channel VT for VC = VB = 0
Fig 10.20*
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28. Project Hints: rp rpc rj rn rnc
Project due date changed to November 18.
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29. References
* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.
**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986
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