1. Basic Instruction Cycle
other
instructions
start
fetch next
instruction
execute
instruction
STOP
stop
instruction
fetch cycle
execute cycle

2. Instruction Cycle with Interrupts
If interrupts
disabled
fetch next
instruction
execute
instruction
STOP
start
stop instruction
fetch cycle
execute cycle
If interrupts
enabled NO
interrupt?
execute interrupt
sequence
YES

3. Interrupt Sequence (review)
save a copy of status register; (SRcopy) ← (SR)
set supervisor mode on (S=1 on SR)
set trace off (T=0 on SR)
determine vector number
save PC on supervisor stack
save SRcopy on supervisor stack
vector address = vector number * 4
(PC) ← (vector address)

4. Interrupt Vector … vector 0
vector 0 = reset (hard reset)
2 longwords in vector table => no vector 1 (unlike all other vectors which are 1 longword)
typically in ROM or supervisor program space
used to load the system or do system recovery
interrupt sequence is different from normal:
Interrupt mask on SR, I2I1I0 ← 111 (highest priority interrupt)
don’t save SR or PC, can’t be trusted
ISR is actually the power up or restart code

5. Interrupt Vector … vectors 2, 3
Function code:
001 user data 010 user program 101 supervisor data 110 supervisor program
Vectors: 2 = bus error, = address error
!! puts additional information on stack to allow debugging
* Instruction = normal instructions, TRAP, TRAPV, CHK, zero divide exception

6. Interrupt Vector … vectors 2, 3
ORG $8000 create an
C 3001 MOVE.W #$3001,A0 illegal addr
MOVE.W (A0),D0 and access
END
e.g. Tutor (unix like IDE)
TUTOR 1.32 > T
PHYSICAL ADDRESS=
ADDR TRAP ERROR
… register dump
e.g. EASy68K (current IDE)
Address Error: Instruction at 8004 accessing address 3001
Execution halted

7. Interrupt Vector … vectors 4-8
vectors 4-8 = programming errors or intentional error handling routines
either put out error message or try to handle (compensate for error)

8. Interrupt Vector … vector 5
ORG $__ ; init vector address
DC.L ZDIV ; for zero divide
ORG $1000
START …
CLR.L D0 ; force divide by zero
DIVU D0,D1 ; D1/D0 …
STOP #$2700
ZDIV LEA Z_ERR,A1 ; addr of error msg
MOVEQ #13,D0 ; task: print string
TRAP #15 ; call monitor
STOP #$2700 ; halt system
Z_ERR DC.B 'System halting: divide by zero',0
END START

9. Interrupt Vector … vector 6
CHK instruction (in reference manual) = CHK <ea>,Dn
check register against bounds:
if Dn < 0 or Dn > upper bound then CHK instruction trap (out of bounds) end if
typically, used to check array index (Dn) against array bounds
MOVE.W INDEX,D1 CHK #max_size,D1

10. Interrupt Vector … vector 7
TRAPV instruction (in ref manual) = TRAPV
trap on signed overflow
if V then TRAPV exception end if
placed immediately after an arithmetic instruction
ADD.L D0,D1 ; add numbers
TRAPV ; check for overflow
MOVE.L D1,NUM ; store result
NOT the same
as TRAP !!

11. Interrupt Vector … vector 9
vector 9 = trace
if trace requested in development environment, T flag set in Status Register
after an instruction has finished executing, system checks the T flag
if T=1, then execute the trace service routine
what does the trace routine do?
for command line systems, dump the registers
for EASy68K, dump PC, IR, instruction opcode e.g. PC=$ CODE=$3010 MOVEW

12. Interrupt Vector … vectors 10,11
vector 10 = Aline (Line 1010) Emulator
vector 11 = Fline (Line 1111) Emulator
allows user to define their own instructions
machine code starts with $A or $F
How would you call these? 33C move.w D0,num A move.l index,A0

13. Interrupt Vector … vectors 24-31
vector 24 = spurious interrupt
no device responds during an interrupt acknowledge cycle (a special class of bus error)
vectors = 7 hardware interrupts
IPL2, IPL1, IPL0 pins on the chip
edge triggered; active low signals
pin combination indicates priority level
000 no interrupt
001 lowest priority interrupt …
111 highest priority interrupt; a "nonmaskable interrupt"
An interrupt request is made to the processor by encoding the interrupt request levels 1–7 on the three interrupt pins.

14. Interrupt Vector … vectors 32-47
vector = TRAP
used to request service from operating system
Traps numbered 0 to 15
how do you pass parameters to trap
in registers
on stack
what if you have more than 16 functions?

15. Interrupt Vector … vector 32
ORG $___
DC.L CLR_REG ;init address vector for Trap 0
ORG $1000
START …
TRAP #0 ; clear registers …
STOP #$2700
CLR_REG LEA R2Z,A1 ; point to zero data area
MOVE.W #15-1,D0 ; adjust cnt for 15 registers
REG_LP MOVE.L #0,(A1)+ ; zero the data area
DBRA D0,REG_LP
MOVEM.L R2Z,D0-D7/A0-A6 ; zero the registers
RTE
R2Z DS.L 15
END START

16. Priority of Interrupts
Group 0 = highest priority group - currently executing instruction aborted - stack contents have additional information - in decreasing priority: -> reset -> bus error -> address error
Group 1 - exception processed at completion of currently executing instruction - in decreasing priority: -> trace (if no other exception happening) -> autovectored interrupts: priority 7 down to 1; other hardware interrupts -> illegal instruction -> privilege violation
Group 2 = exception processed by executing instruction -> TRAP, TRAPV, CHK, Zero divide

17. Multiple Interrupts Sequential Interrupt Processing
Nested Interrupt Processing

18. Multiple Interrupts Printer -> priority 2
generates an interrupt every time it completes a print operation
Communication Unit -> priority 5
generates an interrupt every time a unit of data arrives
Disk -> priority 4
generates an interrupt when data must be handled
User program
Printer ISR
Comm ISR
X Disk
Disk ISR

19. Reading/Expectations
Section 6 - Exception Processing from M /16-/32-Bit Microprocessors User’s Manual [pdf, 184 p; Motorola]
Expectations:
you are responsible for all material in the above section, excluding references to M68010
you should be able to write interrupt service routines for any vector including determining the vector address
you should be able to determine the order of interrupts based on priority and time of arrival for a multiple interrupt system