1. Digital Logic Department of CNET Chapter-6
Registers And Counters

2. Outline of Chapter -6 Registers and Counters Registers Shift Registers
Ripple Counters
Binary Counters
Synchronous Counters

3. 6.1 Registers Clocked sequential circuits Register: Counter:
A group of flip-flops and combinational gates
connected to form a feedback path.
Flip-flops + Combinational gates
(essential) (optional)
Examples: Registers and Counters
Register:
A group of flip-flops, each one of which shares a common clock and is capable of storing one bit information.
Counter:
A register that goes through a predetermined sequence of states.

4. 6.1 Registers A n-bit register n flip-flops capable of storing
n bits of binary information
4-bit register shows in the fig
Constructed with four D-type flip-flops to form a four-bit data storage register.
Fig. 6.1
Four-bit register

5. 6.2 Shift Registers Shift register Simplest shift register
A register capable of shifting its binary information held in each cell to its neighboring cell, in a selected direction, is called a Shift register.
Simplest shift register 1 1 1 1 1 1 1
Fig. 6.3
Four-bit shift register

6. Serial Transfer vs Parallel Transfer
Information is transferred one bit at a time
shifts the bits out of the source register into the destination register
Parallel transfer:
All the bits of the register are transferred at the same time

7. Example: Serial transfer from reg A to reg B
Fig. 6.4
Serial transfer from register A to register B

8. Example: Serial transfer from reg A to reg B

9. Serial addition using D flip-flops1
0101
1010 1 1 1 1 1
0011
?001
Fig. 6.5
Serial adder

10. Serial adder using JK flip-flops
JQ = x y
KQ = x y = (x + y)
S = x  y  Q

11. Second form of serial adder
Circuit diagram
JQ = x y
KQ = x y = (x + y)
S = x  y  Q Ci
Fig. 6.6
Second form of serial adder

12. Types of Universal Shift Register
Unidirectional shift register
Bidirectional shift register
Universal shift register:
has both direction shifts & parallel load/out capabilities

13. Universal Shift Register
Capability of a universal shift register:
A clear control to clear the register to 0.
A clock input to synchronize the operations.
A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right.
A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left.
A parallel-load control to enable a parallel transfer and the n parallel input lines associated with the parallel transfer.
n parallel output lines.
A control state that leaves the information in the register unchanged in the presence of the clock.

14. Example: 4-bit universal shift register
Fig. 6.7
Four-bit universal shift register

15. Fig. 6.7 Four-bit universal shift register (continued)

16. 6.3 Counters
Counter
Definition: A register that goes through a prescribed sequence of states upon the application of input pulses.
Description:
Input pulses may be clock pulses or originate from some external source
The sequence of states may follow the binary number sequence ( Binary counter) or any other sequence of states.
A Counter that follows the binary number sequence is called a binary Counter.
An n-bit binary counter consists of n flip-flops and can count in binary from 0 through 2^n-1.

17. Types of Counters Categories of counters Ripple counters
The flip-flop output transition serves as a source for triggering other flip-flops
 no common clock pulse (not synchronous)
Synchronous counters:
The CLK inputs of all flip-flops receive a common clock

18. Four bit binary ripple counter
Example: 4-bit binary ripple counter
Binary count sequence: 4-bit

19. Four-bit binary ripple counter with T and D flip flops
10 
10
Fig. 6.8
Four-bit binary ripple counter with T and D flip flops

20. 6.4 Synchronous Counters Synchronous counter Design procedure :
A common clock triggers all flip-flops simultaneously.
Design procedure :
Apply the same procedure of synchronous sequential circuit.
Synchronous counter is simpler than general synchronous sequential circuits.

21. 4-bit binary counter Fig. 6.12 Four-bit synchronous binary counter
C_en A0
C_en A0 A1
C_en A0 A1 A2
Fig. 6.12
Four-bit synchronous binary counter