1. Defining LER and Defect Specifications
SFR Workshop
November 08, 1999
Tho Nguyen, Shiying Xiong and J. Bokor
Berkeley, CA
The objective of this work is to understand and model the impact of lithography/etch line-edge roughness in the gate definition layer, on the electrical behavior of short channel transistors

2. Progress Since May Hydrodynamic Model working
3D interaction of Defects
Real LER Simulation

3. Effect of Gate “Errors” on Device Characteristics
Cross-section
Threshold voltage
Turn-off slope
Drive current
Device reliability n+ n+
Edge roughness
Layout views DL
Single defects DW

4. Base Design Channel Doping Selected at 0.4 Volt
Halo Implant Incorporated to Offset Vt rolloff
Threshold Swing Vds = 2V and L = 100nm
DIBL = 70 mV/V for Vds = V
Vt RollOff Characteristics
500
450
Device Length = 200 nm
Channel Length = 100 nm
Channel Width = nm
Buried Oxide = 100 nm
Si Film Thickness = 250Å
Gate Oxide = 30 Å
400
Without Halo Implant
350
With Halo Implant
300
250
0.2
0.4
0.6
0.8 1
1.2
Channel Length (Microns)

5. Real 3D LER Construction and Simulation
Real 3D LER Created by Matlab and incorporated into simulator language
LER defined by bandlimited white spectrum. 2 parameters: RMS roughness, correlation length
Process simulation used for self- aligned S/D doping
Current digitized LER resolution is nm due to limited memory
160

6. Simulation Results 25 % increase in Ioff for 5nm rms roughness
Hydrodynamic model has been successfully turned on in ISE simulator
With hydro on, Ion is ~ 30% higher
Simulations of “real” 3D LER has been successful W = 50nm)
I_V Curves for Different Real 3D LER
Zoom View of Leakage Current
25 % increase in Ioff for 5nm rms roughness
140% increase in Ioff for 9nm rms roughness

7. Simulation Results
Defect shows 3D interaction for channel width less than 100nm
To study LER, we have to use 3D models
Intel Work (T. Linton, et al. 1999):
Simulation of square-wave modulation of LER with Neuman boundary conditions
Shows similar 3D interaction
Leakage control by length adjustment with reasonable Ion reduction

8. Milestone Status June 1999 June 2000
Complete 3D device simulations of mask errors and LER effects in gate-level. Threshold voltage shifts, turn-off characteristics, and saturated drain current will be evaluated.
Status: Late. Student (Tho Nguyen) started Jan Second student (Shiying Xiong) started Sept Expect completion March 2000.
June 2000
Test NMOS devices with programmed mask errors as well as varied LER and compare measured characteristics with simulation results.
Status: Delayed. No company fab support. Will start Microlab run Jan if unable to arrange support from company fab.

9. Proposal for 2000-2002 Simulation Effect of LER on GIDL
Effect of LER in isolation edge
Device reliability
Extend to 50 nm CD
Experiments
Complete gate roughness experiment for 100 nm CD
Isolation roughness experiment
Extend to 50 nm CD??