MICROPROCESSOR ARCHITECTURE REVATI M WAHUL

MICROPROCESSOR ARCHITECTURE REVATI M WAHUL

210245 Microprocessor Architecture
Teaching Scheme Lectures: 3 Hrs/week Practical : 2 Hrs/week Examination Scheme Theory: 50 Marks On Line: 50 Marks Oral: 50 Marks Term Work: 25 Marks

Objectives: The course will provide knowledge to build and program microprocessor based systems. Microprocessor architecture and programming

INTRODUCTION

What is Microprocessor ?
It is a program controlled semiconductor device (IC), which fetches, decode and executes instructions.

2. What are the basic units of a microprocessor ?
The basic units or blocks of a microprocessor are ALU, an array of registers and control unit.

3.what is Software and Hardware?
The Software is a set of instructions or commands needed for performing a specific task by a programmable device or a computing machine. The Hardware refers to the components or devices used to form computing machine in which the software can be run and tested. Without software the Hardware is an idle machine.

5. What are machine language and assembly language programs?
The software developed using 1's and 0's are called machine language programs. The software developed using mnemonics are called assembly language programs.

4. What is assembly language?
The language in which the mnemonics (short -hand form of instructions) are used to write a program is called assembly language. The manufacturers of microprocessor give the mnemonics.

6. What is the drawback in machine language and assembly language programs?
The machine language and assembly language programs are machine dependent. The programs developed using these languages for a particular machine cannot be directly run on another machine .

7. Define bit, byte and word.
A digit of the binary number or code is called bit. Also, the bit is the fundamental storage unit of computer memory. The 8-bit (8-digit) binary number or code is called byte and 16-bit binary number or code is called word. (Some microprocessor manufactures refer the basic data size operated by the processor as word).

8. What is a bus? Bus is a group of conducting lines that carries data, address and control signals.

9. What is the function of microprocessor in a system?
The microprocessor is the master in the system, which controls all the activity of the system. It issues address and control signals and fetches the instruction and data from memory. Then it executes the instruction to take appropriate action.

Microprocessor based system
CPU on a single chip CPU consists of control unit, ALU and registers. Microprocessor based system -CPU -Input -Output -Memory

What are microprocessor-based systems?
Memory Output units Input Bus Microprocessor Control unit Datapath ALU Reg.

Microprocessor-based systems are electrical systems consisting of microprocessors, memories, I/O units, and other peripherals. Microprocessors are the brains of the systems. Microprocessors access memories and other units through buses. The operations of microprocessors are controlled by instructions stored in memories

MICRO PROCESSER MICRO CONTROLLER CP It is a CPU • It is a single chip
• Consists Memory, I/o ports It is a CPU Memory, I/O Ports to be connected externally CP CPU MEMORY MEMORY I/O PORTS I/O PORTS

Reference Material

Text Books 1. (Paperback) Microprocessor Handbook, Chris H. Pappas, William H. Murray 2. Professional Multicore Programming: Design and implementation for C++ Developers, Wiley India Edition, ISBN: 3 Intel® 64 and 32 bit Architectures Software developer’s Manual, Volume –I, Intel, (Digital Content PDF, pdf) 4. Introduction to 64 bit Intel Assembly Language Programming for Linux, 2nd Edition, Ray Seyfarth, ISBN10: , ISBN-13: , 2012

References 1. Intel 64 and IA-32 bit architectures Software Developer’s Manual, Volume 3A, Intel, (Digital Content PDF: pdf) 2 Ensuring Development Success By Understanding and Analyzing Assembly Language, Intel 2009 (Digital Content PDF: pdf) 3. Assembly Language Step-by-step: Programming with Linux, 3rd Edition, Jeff Duntemann, Wiley ISBN: , ISBN-13: , 2009

MA Syllabus Unit I 80386DX Architecture 8 Hrs
History of 8086 microprocessor, Concept of segmentation in 8086, 8086 Register block diagram, 80386DX functional Block Diagram, PIN Description, Register set, Flags, Physical address space, Data types

MA Syllabus Unit II Memory Management Unit and Segment Description and Paging 10 Hrs 80386Dx descriptor Tables GDT, LDT, IDT, descriptor cache, Code, data and stack descriptors, system descriptors, privilege levels, Segmentation in 80386DX, comparison of segmentation with 8086, paging, TSS, Nested Tasks, Operating in Real Mode, Protected Mode, Virtual 86 mode, Virtual addressing

MA Syllabus Unit III Pipelined Architecture 6 Hrs
Non-pipelined machine cycle, pipelined machine cycle.

MA Syllabus Unit IV Assembly Language Programming 8 Hrs
80386DX instruction set, setting protected mode, setting v86 mode, Real mode programming

MA Syllabus Unit V New Architectures 4 Hrs
What is multicore?, Multicore Architectures, The Software Developer’s Viewpoint, The Bus Connections, Single Core to Multicore.

MA Syllabus Unit VI Multicore Designs 12 Hrs
Intel 64bit Architecture: Block Diagram, Basic Execution Environment, Data Types, Specific advances: Instruction set, Intel Microarchitecture code name Nehalem, SIMD Instructions, Hyper threading Technology, Virtualization Technology (Refer TB3) Systems Programming, Multiple Processor Management (Refer RB1)

MA Lab Syllabus Group A (Mandatory) 1.
Group A (Mandatory) 1. Write ALP to print “Hallo World!” Program using 16, 32 and 64-bit model and segmentation. 2. Write an ALP to accept ten 32-bit and 64 bit Hexadecimal numbers from user and store then in data segment table and display then numbers. 3 Write an ALP to accept a string and to display it’s length. 4 Write an ALP to perform arithmetic and logical operations using ‘n’, 32-bit and 64-bit numbers stored in an array using 64 bit register operations. 5 Write an ALP to perform memory segment and register load/store operations using different addressing modes. 6 Write an ALP to program to use GDTR, LDTR and IDTR in Real Mode.

MA Lab Syllabus Group B (at least 6) 1
Group B (at least 6) 1 Write an ALP to fond the largest of given byte/Word/Dword/64-bit numbers 2 Write C program using ALP instructions to convert Binary to decimal number. 3 Write ALP using to read and display the table content pointed by GDTR/LDTR and IDTR 4 Write ALP to demonstrate the use of paging tables 5 Write C program using an ALP instructions to set to use ETP (Extended page tables) with Core i3/i5/i7 Nehalem processors 6 Write a switch case driven ALP to perform 64-bit hexadecimal arithmetic operations (+,-,*, /) using suitable macros. Define procedure for each operation.

MA Lab Syllabus 7 Write an ALP to read command line arguments passed to a program. 8 Write an ALP to count no. of positive and negative numbers from the array. 9 Write ALP to identify CPU type and FPU type. 10 Write ALP to find average of n numbers stored in memory 11 Write program to read & display contents of file 12 Write a program to calculate area of circle using (co-processor) 13 Write a program to switch between real mode and protected mode 14 Write an ALP password program that operates as follows: a. Do not display what is actually typed instead display asterisk (“*”). If the password is correct display, “access is granted” else display “Access not Granted” 15 Write program to read & display ASCII contents of a file 16 Write an ALP to convert 64-Bit Big-Endian Number to Little-Endian Number

MA Lab Syllabus Group C (at least One) 1
Group C (at least One) 1 Write a ALP to define two tasks and execute them on different CPU cores. 2 Write a password program that operates as follows: b. Do not display what is actually typed instead display asterisk (“*”). c. If the password is correct display, “access is granted” else “sound the alarm”. 3 Write ALP to switch from real mode to protected mode and display the values of GDTR, LDTR, IDTR, TR and MSW Registers. 4 Write a program for cache memory simulation. Consider 16kb of main memory, 128 byte of two way set associative caches. Assume 4 byte cache line. Find hit or miss in a cache line. If miss occurs line should be replaced in the cache using LRU technique. 5 Write a program to implement the multitasking application

Home Work Define a microprocessor.
Describe how microprocessor connects to the external world How languages are executed on microprocessors.

Assembly Language ??????

What is Machine Language?
Each personal computer has a microprocessor that manages the computer's arithmetical, logical and control activities. Each family of processors has its own set of instructions for handling various operations like getting input from keyboard, displaying information on screen and performing various other jobs. These set of instructions are called 'machine language instruction'.

What is Assembly Language?
Processor understands only machine language instructions which are strings of 1’s and 0’s. However machine language is too obscure and complex for using in software development. So the low level assembly language is designed for a specific family of processors that represents various instructions in symbolic code and a more understandable form.

Assembly Language Programming
Assembly language is a low-level programming language . It is for a computer, or other programmable device specific to a particular computer architecture. Assembly language is converted into executable machine code by a utility program referred to as an assembler like NASM [Netwide Assembler], MASM, TASM etc.

Advantages of Assembly Language
An understanding of assembly language provides knowledge of: Interface of programs with OS, processor and BIOS; Representation of data in memory and other external devices; How processor accesses and executes instruction; How instructions accesses and process data; How a program access external devices.

Advantages of Assembly Language (2)
Other advantages of using assembly language are: It requires less memory and execution time; It allows hardware-specific complex jobs in an easier way; It is suitable for time-critical jobs;

Assembly Basic Syntax An assembly program can be divided into three sections: The data section The bss section The text section

The data Section The data section is used for declaring initialized data or constants. This data does not change at runtime. We can declare various constant values, file names or buffer size etc. in this section. The syntax for declaring data section is: section .data

The bss Section bss: block started by symbol
The bss section is used for declaring variables. The syntax for declaring bss section is: section .bss

The text section section .text global _start _start:
The text section is used for keeping the actual code. This section must begin with the declaration global main, which tells the kernel where the program execution begins. The syntax for declaring text section is: section .text global _start _start:

Comments Assembly language comment begins with a semicolon (;).
It may contain any printable character including blank. It can appear on a line by itself, like: ; This program displays a message on screen Or, on the same line along with an instruction, like: add eax ,ebx ; adds ebx to eax

Basic Features of PC Hardware
The main internal hardware of a PC consists of the processor, memory and the registers. The registers are processor components that hold data and address. To execute a program the system copies it from the external device into the internal memory. The processor executes the program instructions. The fundamental unit of computer storage is a bit; it could be on (1) or off (0).

Data Types Fundamental data types Bytes Words doublewords

The processor supports the following data sizes:
Word: a 2-byte data item Doubleword: a 4-byte (32 bit) data item Quadword: an 8-byte (64 bit) data item Paragraph: a 16-byte (128 bit) area Kilobyte: 1024 bytes Megabyte: 1,048,576 bytes

The Binary Number System
The Hexadecimal Number System

Skip Starts The PPTs till Skip Ends are not conducted.

Addressing Data in Memory
The process through which the processor controls the execution of instructions is referred as the fetch-decode-execute cycle, or the execution cycle. It consists of three continuous steps: Fetching the instruction from memory Decoding or identifying the instruction Executing the instruction

The processor stores data in reverse-byte sequence
The low-order byte is stored in low memory address and high-order byte in high memory address. So if processor brings the value 0725H from register to memory, it will transfer 25 first to the lower memory address and 07 to the next memory address.

Example The processor may access one or more bytes of memory at a time. Let us consider a hexadecimal number 0725H. This number will require two bytes of memory. The high-order byte or most significant byte is 07 and the low order byte is 25.

x : Memory Address When the processor gets the numeric data from memory to register, it again reverses the bytes.

Memory Address There are two kinds of memory addresses:
An absolute address - a direct reference of specific location. The segment address (or offset) - starting address of a memory segment with the offset value

Assembly Language Statements
Assembly language programs consist of three types of statements: Executable instructions or instructions Assembler directives or pseudo-ops Macros

The executable instructions or simply instructions tell the processor what to do. Each instruction consists of an operation code (opcode). Each executable instruction generates one machine language instruction. The assembler directives or pseudo-ops tell the assembler about the various aspects of the assembly process. These are non-executable and do not generate machine language instructions. Macros are basically a text substitution mechanism.

Syntax of Assembly Language Statements
Assembly language statements are entered one statement per line. Each statement follows the following format: [label] mnemonic [operands] [;comment] The fields in the square brackets are optional. A basic instruction has two parts: The first one is the name of the instruction (or the mnemonic) which is to be executed, and The second are the operands or the parameters of the command.

Examples ADD AH, BH ; Add the content of the BH register into the AH register MOV TOTAL, 48 ; Transfer the value 48 in the memory variable TOTAL INC COUNT ; Increment the memory variable COUNT

Assignment #1i Write 32-bit assembly language program to display the string “Hello World” on the screen

section .text ;code segment global _start ;must be declared for linker _start: ;tell linker entry point mov eax,4 ;system call number (sys_write) mov ebx,1 ;file descriptor (stdout) mov ecx,msg ;message to write mov edx,len ;message length int 0x80 ;call kernel mov eax,1 ;system call number (sys_exit) int 80h ;call kernel section .data ;data segment msg db ‘Hello, world!',0xa ; string len equ $ - msg ;length of string

Assignment #1ii Write 64-bit assembly language program to display the string “Hello World” on the screen

section .text global _start _start: mov rax,01 ;write system call mov rdi,01 mov rsi,msg mov rdx,msglen syscall mov rax,60 ;exit system call xor rdi,rdi section .data msg db 'Hello World' , 0xa msglen : equ $-msg

Compiling and Linking an Assembly Program in NASM
Type the above code using a text editor and save it as p1.asm. To assemble the program, type nasm -f elf64 p1.asm If there is any error, you will be prompted about that at this stage. Otherwise an object file of your program named p1.o will be created. 3.To link the object file and create an executable file named hello, type ld -o p1 p1.o 4.Execute the program by typing ./p1

Memory Segments A segmented memory model divides the system memory into groups of independent segments, referenced by pointers located in the segment registers. Each segment is used to contain a specific type of data. One segment is used to contain instruction codes, another segment stores the data elements, and a third segment keeps the program stack.

Assembly Variables NASM provides various define directives for reserving storage space for variables. The define assembler directive is used for allocation of storage space. It can be used to reserve as well as initialize one or more bytes.

1. Allocating Storage Space for Initialized Data
The syntax for storage allocation statement for initialized data is: [variable-name] define-directive initial-value [,initial-value]... Where, variable-name is the identifier for each storage space. The assembler associates an offset value for each variable name defined in the data segment. There are five basic forms of the define directive:

Following are some examples of using define directives:
choice DB 'y' number DW 12345 neg_number DW big_number DQ real_number1 DD 1.234 real_number2 DQ

Note Each byte of character is stored as its ASCII value in hexadecimal Each decimal value is automatically converted to its 16-bit binary equivalent and stored as a hexadecimal number Processor uses the little-endian byte ordering Negative numbers are converted to its 2's complement representation Short and long floating-point numbers are represented using 32 or 64 bits, respectively

2.Allocating Storage Space for Uninitialized Data
The reserve directives are used for reserving space for uninitialized data. The reserve directives take a single operand that specifies the number of units of space to be reserved. Each define directive has a related reserve directive. There are five basic forms of the reserve directive:

Multiple Initializations
The TIMES directive allows multiple initializations to the same value. For example, an array named marks of size 9 can be defined and initialized to zero using the following statement: marks TIMES 9 DW 0 The TIMES directive is useful in defining arrays and tables.

3.Multiple Definitions We can have multiple data definition statements in a program. For example: choice DB 'Y' ;ASCII of y = 79H number1 DW ;12345D = 3039H number2 DD ; D = 75BCD15H The assembler allocates contiguous memory for multiple variable definitions.

Assembly Constants Directives provided by NASM that define constants are: EQU %assign %define

The EQU Directive The EQU directive is used for defining constants.
The syntax of the EQU directive is as follows: CONSTANT_NAME EQU expression For example, TOTAL_STUDENTS equ 50 We can then use this constant value in our code, like: mov ecx, TOTAL_STUDENTS cmp eax, TOTAL_STUDENTS The operand of an EQU statement can be an expression: LENGTH equ 20 WIDTH equ 10 AREA equ length * width

The %assign Directive The %assign directive can be used to define numeric constants like the EQU directive. This directive allows redefinition. For example, we may define the constant TOTAL as: %assign TOTAL 10 Later in the code we can redefine it as: %assign TOTAL 20 This directive is case-sensitive.

The %define Directive The %define directive allows defining both numeric and string constants. This directive is similar to the #define in C. For example, we may define the constant PTR as: %define PTR [EBP+4] The above code replaces PTR by [EBP+4]. This directive also allows redefinition and it is case sensitive.

Program displays 9 asterisks on the screen:
section .text global _start: ;must be declared for linker (ld) _start: ;tell linker entry point mov eax,4 ;system call number (sys_write) mov ebx,1 ;file descriptor (stdout) mov ecx, stars ;message to write mov edx,9 ;message length int 80h ;call kernel mov eax,1 ;system call number (sys_exit) section .data stars times 9 db '*' When the above code is compiled and executed, it produces following result: *********

Skip Ends

UNIT I DX ARCHITECTURE

Topics To Cover Functional Block Diagram PIN Description Register set
History of 8086 microprocessor Concept of Segmentation in 8086 8086 Register, block diagram 80386DX Functional Block Diagram PIN Description Register set Flags Physical address space Data types

History of the Microprocessor
In the year 1969 the microprocessor was called the “Micro computer chip” and this was named by Busicom. The term microprocessor was developed until 1972.

Microprocessor Another Source
defined in Webster Integrated circuit that contains the entire central processing unit of a computer on a single chip. Another Source Microprocessor is a device that integrates the functions of the CPU in a computer onto the semiconductor chip.

Essentials Microprocessors contain core essentials
of a computer system. Memory unit ALU Control unit Interrupt / Exception controller Internal cache

Essentials The memory unit and interforce enables the microprocessor to sustain a two-way communication with semiconductor, and chips that stores the program and data. This supports memory, writes and reads blocks of wards. The internal cache is a memory chip- stores and holds recently used information and data. Which will be used in the future. The interrupt and exception controller enables the microprocessor. Takes action to the external environment. The control unit operates the outer units and fetches instructions from a chip cache and execute them.

The integrated circuit also known as the (IC) was invented in 1958 by a man known as Jack S. Kilby. Kilby worked for Texas instruments . While Kilby was working for TI he was designing micro modules for the military, these micro modules connected germanium wafers to discreet components collectively by stacking the wafers one on top of another. While Kilby was working on the modules he thought this procedure was ridiculous and unnecessarily complicated and thought the germanium was engineered properly and it could act as components to stimuli . This is when the first IC was born.

Intel In the year 1969, 4004 instruction set had been defined as a computer terminal corporation, also known as the (CTC). This processor asked Intel to develop an LSI chip for the new and intelligent terminals that were being developed. Hoff and a man by the name of Stan Mazor put the whole processor on one chip. The MCS-4 was made in April of This CPU chip launched and became the furthermost success yet.

Intel Intel 8080 was developed in April of It was not available to customers at this time because of the design chip into the products and wasn’t ready. The 8080 processor had over 4,500 transtors and this number was doubled in the 4004 which was addressed to 64 Kbytes (memory). The speed was down because of the use of electron doped technology in assessment to hole doped MOS transistors. In 1978 Intel produced the first ever 16 bit processor the “8086” it was well-matched with the 8080, the 8086 was the most effective processor thus far.

Competitors and the early years Even though Intel invented the microprocessor and had the company grow from a 3 employee workshop to a 20,000 Employee Company didn’t mean they were the only ones developing the microprocessor. In July of Microprocessors were available, over the next few years the number increased rapidly. In 1976 it became 54. The second processor was available late in the year of 1972 developed by Rockwell. In 1974 Texas Instrument came out with the TMS1000 which was the first microprocessor to contain its very own RAM and ROM on chip.

Competitors and the early years The success of the Intel 808 Zilog and Motorola, made the two produce competing chips. Motorola produced the 6800 which was very group orientated hardware and as popular as the chip had seemed to be it, it fell through underdeveloped which was designed by a group of engineers that had left Intel previously. These two men were Fredrico Faggin and Masatoshi Shima who had previously designed the 8080 and 4004 for Intel. After Motorola introduced the first 16 bit processor they came out with a chip that addressed 16 megabytes and was competent to act like a 32 bit processor. They were and are found in Amga and, Macintosh computers.

Competitors and the early years Intel’s very first microprocessor contained so much processing power that it was considered the “most powerful” computer in the world at the time. This computer microprocessor was the “ENIAC” and it filled an entire room. Intel released the i386 processor in the 1990s. This microprocessor was the first commercially available 32-bit processor. The i386 was made to multitask by running more then one program at a time mainly on a desktop computer. The Intel Pentium processor was released in 1993 making it the first available microprocessor capable of executing two instructions for every clock cycle. Intel’s serious competitor today is the AMD (Advanced Micro Devices).

The microprocessor came about when the size of the central processing unit reduced from 32 bits to 4, making it sufficient for it to fit into the IC. When more then one microprocessor serves as a processing unit, it is then called a CPU, which is frequent in a handheld device or computer. The evolution of the microprocessor has been said to have followed Moore’s Law, increasing performances every year. This has been proven since the 1970s. Power is continuously increased, which has led to the ascendancy of microprocessors, over every computer. Mainly everything in day’s world uses a Microprocessor.

16 bit design The very first multi-chip was a 16 bit microprocessor was TI’s TMS 9900 and was similar in temperament with TIs TI990 minicomputers. This chip was packaged in ceramic 64 pin DIP packages, and was designed to battle with the Intel The WDC (Western Design Center, Inc introduced the CMOS bit which was an upgrade of the WDC CMOS 65C02. This was developed in 1984 and was the core of the Apple IIgs, and later on Super Nintendo System. This made it a very admired design. The very first single chip was a 32 bit processor that was the AT&T Bell Labs BELLMAC 32A, this came about in 1980 and was produced in The most famous 32 bit design is the MC6800 made in The 68K had 32 bit registers and only used 16 bit internal paths and 16 external for pin count. It was very high speed and large.

RISC In the 1980s and 1990s RISC (Reduced Instruction Set Computer) made its appearance. It was made for Unix workstations and purpose machines, but today are widespread in all roles set aside desktop computers. RISC today designs are based on MIPS, PowerPC and ARM for majority of computing devices

Facts 44 Billion dollars worth of Microprocessors were made in 2003 as well as sold. Most was spent on laptop and or desktop computers it takes about 0.2 % of the CPU’s sold. Almost 56% of CPUs sold are 8 bit microcontrollers. Less the 10 % of CPUs sold are 32 bit or more. Most are sold in house hold appliances such as vacuums, TVs, Microwaves, toasters and so forth.

1 Bit = Binary Digit 8 Bits = 1 Byte Bytes = 1 Kilobyte Kilobytes = 1 Megabyte Megabytes = 1 Gigabyte Gigabytes = 1 Terabyte Terabytes = 1 Petabyte Petabytes = 1 Exabyte - Exabytes = 1 Zettabyte Zettabytes = 1 Yottabyte Yottabytes = 1 Brontobyte

2 Types of Models Programmer’s Model: Includes Features like internal registers, address , data & control buses i.e. model to program the device Hardware Model : Shows Pin diagram and the signals to / from i.e. theses pins are to understand how a microcomputer system is built around.

8086 Microprocessor Features
It is a 16-bit μp. A 40 pin dual in line package 16 bit data bus and 20 bit address bus 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). 8086 is designed to operate in two modes, Minimum and Maximum.

8086 Microprocessor Features
It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. When 8086 is reset, the processor fetches its first instruction from address FFFF0 H. On the PC, this address enables the motherboard’s system ROM, which begins the process of booting DOS.

Architecture Of 8086

Internal Architecture of 8086
• 8086 has two blocks BIU and EU. • The BIU performs following bus operations : instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. • The instruction bytes are transferred to the instruction queue. • EU executes instructions from the instruction system byte queue.

Internal Architecture of 8086 (cont..)
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

BIU contains : EU contains: Instruction queue, Segment registers,
Instruction pointer, Address adder. EU contains: Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

Bus Interface Unit: • It provides a full 16 bit bidirectional data bus and 20 bit address bus. • The bus interface unit is responsible for performing all external bus operations.

Specifically BIU has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. • The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

These prefetched instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

This queue permits prefetch of up to six bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

The EU accesses the queue from the output end.
It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory, BIU is idle.

• These intervals of no bus activity, which may occur between bus cycles are known as Idle state. • If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.

The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

EXECUTION UNIT The EU is responsible for decoding and executing all instructions. • The EU : extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write cycles to memory or I/O and perform the operation specified by the instruction on the operands. • During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.

• If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. • When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. • Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

Revise : 2 Independent Functional Units
BIU (bus interface unit) sends out addresses, fetches instructions from memory, reads data from ports and memory, and writes data to ports and memory. In other words, the BIU handles all transfers of data and addresses on the buses for the execution unit. EU (execution unit) of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions, and executes instructions.

The 8086 has a 20-bit Address Bus
With 20 bits, 1,048,576 different combinations are available. Each memory location is assigned a different combination. Each memory location is 1-byte wide. Therefore, the memory space of the 8086 consists of 1,048,576 bytes or 524, bit words.

Problem The 8086 has a 20-bit address bus. Therefore, it can access 1,048,576 bytes of memory. How many bits and how many HEX digits are required to access 1M memory? 2N = 1M (where N is in bits) N = 20 bits = 20/4 = 5 HEX digits

Positional Notation (Hex Digits)

Problem Continued But each register is only 16 bits (4 HEX digits) wide. How are all of the locations accessed? Segmented Memory – all of memory is divided into 64-kByte segments. (4 HEX digits (16 bits) can access 64k different locations) 216  64k

Segmented Memory Within the 1 MB of memory, the 8086 defines KB memory blocks. DS: E CS: B300 SS: ES: 5D27 7FFFF The segment registers point to location 0 of each segment. (The base address)

Segment Register Defaults

Segments/ Segmentation
Segments are variable-sized areas of memory used by a program containing either code or data. Segmentation provides a way to isolate memory segments from each other. This permits multiple programs to run simultaneously without interfering with each other. A segment selector is a 16-bit value stored in a segment register. A logical address is a combination of a segment selector and an offset(16-bit for 8086).

Logical Addresses Using a virtual-8086 mode, we can determine the “physical address” by adding the offset to the base.

Determining the Physical Address from a Logical Address
Shift the segment value left 4 bits (add a zero to the right), then add the offset 3D7F:023C  3DA2Ch

Real-Mode Addessing In real mode addressing, the lowest 640K of memory is used by both the operating system and application programs. Video memory and hardware controllers have reserved memory locations. C0000h-FFFFFh are reserved for system ROM. IVT (Interrupt Vector Table) is at first 1024 bytes of memory ( FFFh)

Memory Map for an 80x86 computer running MS-DOS

Memory Banks Even though the 8086 has a 16-bit data bus, it is byte addressable. Memory is divided into two 8-bit banks Even Addresses Odd Addresses BE0 BE1

Memory Chip Organization
Memory chips are usually defined as a k x n device (k=#locations, n=number of cells per location) Examples 16 x 1 (16M bits) 4M x 4 (4M nibbles) 2M x 8 ( 2M bytes) 1M x 16 (16 M words) SRAM and ROM are typically arranged x8 (byte wide)

Internal Registers of 8086 The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers. The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags.

Internal Registers of 8086 (cont..)
Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code Segment register :CS Stack Segment register :SS Data Segment register :DS Extra Segment register :ES

Code segment CS is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.

Stack segment SS is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.

Data Segment DS is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.

Extra Segment ES is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for arithmetic and logic operations.
The general registers are: Accumulator Base Register Count Register Data Register

• Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.

Base Register Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.

Count Register Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation.

Data Register Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

The following registers are both general and index registers: Stack Pointer Base Pointer Source Index Destination Index

Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.

Other registers: Instruction Pointer (IP) is a 16-bit register. Flags

Flag Register Flags is a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand. Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.

• Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction. • Sign Flag (SF) - set if the most significant bit of the result is set. • Zero Flag (ZF) - set if the result is zero.

Internal Registers of 8086 • Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register. • Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. • Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation.

8086 Pin Diagram

8086 Modes 2 Modes of operation Minimum Mode (Single processor mode)
Maximum Mode (Multiprocessor mode)

8086 Signal Categorization
The signals having common functions in min and max mode The signals for minimum mode The signals for maximum mode

In the minimum mode ,the CPU is configured for small, single – processor systems and CPU itself provides all control signals. In maximum mode, an Intel 8288 Bus Controller, rather than CPU, provides the control signal outputs.

M/IO# – Memory/IO# This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge”

•INTA# -Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. •ALE – Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated.

•DT/R# – Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. •DEN – Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during ‘ hold acknowledge’ cycle.

HOLD, HLDA- Acknowledge
When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle. At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized.

HOLD, HLDA- Acknowledge
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided: 1.The request occurs on or before T2 state of the current cycle. 2.The current cycle is not operating over the lower byte of a word. 3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A Lock instruction is not being executed.

Queue Status Lines These lines give information about the status of the code-prefetch queue. These are active during the CLK cycle after which the queue operation is performed. These are encoded as shown in Table (lastslide)

Instruction Pipelining
The 8086 architecture has a 6-byte instruction prefetch queue. Thus even the largest (6-bytes) instruction can be prefetched from the memory and stored in the prefetch queue. This results in a faster execution of the instructions. In 8085, an instruction (opcode and operand) is fetched, decoded and executed and only after the execution of this instruction, the next one is fetched. By prefetching the instruction, there is a considerable speeding up in instruction execution in 8086. This scheme is known as instruction pipelining.

Instruction Prefetch Queue
At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty and the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even. The first byte is a complete opcode in case of some instructions (one byte opcode instruction) and it is a part of opcode, in case of other instructions (two byte long opcode instructions), the remaining part of opcode may lie in the second byte. But invariably the first byte of an instruction is an opcode. These opcodes along with data are fetched and arranged in the queue.

Decoding….. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is updated. The microprocessor does not perform the next fetch operation till at least two bytes of the instruction queue are emptied. The instruction execution cycle is never broken for fetch operation. After decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte.

If it is single opcode byte, the next bytes are treated as data bytes depending upon the decoded instruction length, other wise, the next byte in the queue is treated as the second byte of the instruction opcode. The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least, two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.

RQ#/GT0#, RQ/GT1-ReQuest/Grant
Used by other local bus masters in maximum mode To force the processor to release the local bus at the end of the processor's current bus cycle Each of the pins is bidirectional with RQ#/GT0# having higher priority than RQ#/ GT1# RQ#/GT# pins have internal pull-up resistors and may be left unconnected.

The request/ grant sequence is as follows: 1
The request/ grant sequence is as follows: 1. A pulse one clock wide from another bus master requests the bus access to During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the "hold acknowledge" state at next clock cycle. The CPU's bus interface unit is likely to be disconnected from the local bus of the system. 3. A one clock wide pulse from the another master indicates to 8086 that the 'hold‘ request is about to end and the 8086 may regain control of the local bus at the next clock cycle.

Thus each master to master exchange of the local bus is a sequence of 3 pulses.
There must be at least one dead clock cycle after each bus exchange. The request and grant pulses are active low. For the bus requests those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD, and HLDA in minimum mode.

Content beyond Syllabus: IPS Measures
Instructions per second (IPS) is a measure of a computer's processor speed. thousand instructions per second (kIPS), million instructions per second (MIPS), Giga instructions per second (GIPS), million operations per second (MOPS)

8088 8-Bit Data Bus Interface 16-Bit Internal Architecture
Direct Addressing Capability to 1 Mbyte of Memory Direct Software Compatibility with 8086 CPU 14-Word by 16-Bit Register Set with Symmetrical Operations 24 Operand Addressing Modes

8088 Use of an external data bus that is 8 bit wide
This forces 8088 to access memory twice as often as 8086 Results in performance penalty in terms of execution speed.

80186 A souped –up version of 8086 Contained special hardware such as programmable timers, counters, interrupt controllers, and address decoders Never used in PC Ideal for the systems that required a minimum of hardware.

80186 The 80186 is a very high integration 16-bit microprocessor.
It combines 15–20 of the most common microprocessor system components onto one chip while providing twice the performance of the standard 8086. The is object code compatible with the 8086/8088 microprocessors and adds 10 new instruction types to the 8086/8088 instruction set.

80286 High performance with memory management and protection
Does not contain internal DMA controllers, timers and other enhancements Concentrates on features needed to implement multitasking Multitasking: An operating system environment that allows many programs or tasks to run seemingly simultaneously. A 24 bit address bus so the processor can access upto 16MB of storage

The Intel® 286 Processor (1982)
The Intel 286 processor introduced protected mode operation into the IA-32 architecture. Protected mode uses the segment register content as selectors or pointers into descriptor tables. Descriptors provide 24-bit base addresses with a physical memory size of up to 16 MBytes, support for virtual memory management on a segment swapping basis, and a number of protection mechanisms. These mechanisms include: • Segment limit checking • Read-only and execute-only segment options • Four privilege levels

The Intel386DX™ Processor (Oct 1985)
First 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers for use both to hold operands and for addressing. The lower half of each 32-bit Intel386 register retains the properties of the 16-bit registers of earlier generations, permitting backward compatibility. Provides a virtual-8086 mode that allows for even greater efficiency when executing programs created for 8086/8088 processors. In addition, the Intel386 processor has support for: • A 32-bit address bus that supports up to 4-GBytes of physical memory • A segmented-memory model and a flat memory model • Paging, with a fixed 4-KByte page size providing a method for virtual memory management • Support for parallel stages

Source : Wiki In May 2006, Intel announced that production would stop at the end of September 2007. Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems. Such systems using an or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones also used the processor, such as BlackBerry 950 and Nokia 9000 Communicator.

Features of 80386 The memory management section of 80386 supports the
virtual memory, paging and four levels of protection, maintaining full compatibility with The offers a set of 8 debug registers DR0-DR7 for hardware debugging and control. The has on-chip address translation cache. The concept of paging is introduced in that enables it to organize the available physical memory in terms of pages of size 4Kbytes each, under the segmented memory. The can be supported by for mathematical data processing.

80386 32-bit microprocessor forms the basis for a high-performance 32-bit system Features : multitasking support, memory management, pipelined architecture, address translation caches, and a high-speed bus interface [all on one chip] integration of features speeds the execution of instructions Paging and dynamic data bus sizing can each be invoked selectively , making the suitable for a wide variety of system designs and user applications.

80386 32-bit wide internal and external data paths
Eight general-purpose 32-bit registers The instruction set offers 8-, 16-, and 32-bit data types The processor outputs 32-bit physical addresses directly, for a physical memory capacity of four gigabytes.( 232) The processor addresses up to four gigabytes of physical memory and 64 terabytes (2^46) of virtual memory.

80386 Pin Diagram

Signal Descriptions of 80386
CLK2: The input pin provides the basic system clock timing for the operation of D0 – D31: These 32 lines act as bidirectional data bus during different access cycles. A31 – A2: These are upper 30 bit of the 32- bit address bus. BE0# toBE3 #: The 32- bit data bus supported by and the memory system of can be viewed as a 4- byte wide memory access mechanism. The 4 byte enable lines BE0# to BE3#, may be used for enabling these 4 blanks. Using these 4 enable signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously.

5. ADS#: The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The does not have any ALE signals and so this signals may be used for latching the address to external latches. 6. READY#: The ready signals indicate to the CPU that the previous bus cycle has been terminated and the bus is ready for the next cycle. The signal is used to insert WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU.

7. VCC: . These are system power supply lines.
8. VSS: These return lines for the power supply. 9. BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with the 32 bit wide data bus. Successive 16 bit bus cycles may be executed to read a 32 bit data from a peripheral.

10.HOLD: The bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted. 11. HLDA: The bus hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU. 12. BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy with the allocated task. 13. ERROR#: The error input pin indicates to the CPU that the coprocessor has encountered an error while executing its instruction.

14.PEREQ: The processor extension request output signal indicates to the CPU to fetch a data word for the coprocessor. 15.INTR: This interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register. 16.NMI: A valid request signal at the non-maskable interrupt request input pin internally generates a non- maskable interrupt of type2. 17.RESET: A high at this input pin suspends the current operation and restart the execution from the starting location. 18.N / C : No connection pins are expected to be left open while connecting the in the circuit.

19. W/R#: The write / read output distinguishes the write and read cycles from one another. 20. D/C#: This data / control output pin distinguishes between a data transfer cycle from a machine control cycle like interrupt acknowledge. 21. M/IO#: This output pin differentiates between the memory and I/O cycles. 22. LOCK#: The LOCK# output pin enables the CPU to prevent the other bus masters from gaining the control of the system bus. 23. NA#: The next address input pin, if activated, allows address pipelining, during bus cycles.

80386 PIN DESCRIPTION TABLE The table lists a brief description of each pin on the Intel386 DX. The following definitions are used in these descriptions: # :The named signal is active LOW. I :Input signal. O :Output signal. I/O :Input and Output signal. - : No electrical connection.

REGISTER OVERVIEW The Intel386 DX has 32 register resources in the
following categories: General Purpose Registers Segment Registers Instruction Pointer and Flags Control Registers System Address Registers Debug Registers Test Registers.

Note The registers are a superset of the 8086, and registers, so all 16-bit 8086, and registers are contained within the 32-bit Intel386DX.

Register set diagram shows all of Intel386 DX base architecture registers, which include the general address and data registers, the instruction pointer, and the flags register. The contents of these registers are task-specific, so these registers are automatically loaded with a new context upon a task switch operation.

Fig : Intel386TM DX Base Architecture Registers

EAX EBX ECX EDX EBP ESI EDI AH AL AX BH BL BX CH CL CX DH DL DX BP SI DI Accumulator Base Count Data Base Pointer Source Index Destination Index Note : E in the register stands for extended

CS DS SS ES FS GS Code Segment Data Segment Stack Segment Extra Segment

IP SP FLAGS EIP ESP EFLAGS Instruction Pointer Stack Pointer

The 80386 microprocessor contains 4 data registers referred to as
1.EAX 2. EBX 3.ECX EDX All are 32 bits wide. The lower 16 bits of each register are called AX BX,CX, and DX and may be split up into halves of 8 bits each. 5 other 32-bit registers are available for use as pointer or index registers. 1. ESP 2.EBP 3.ESI 4.EDI 5. EIP None of the 5 may be divided up in a manner similar to the data registers. EAX, EBX, ECX, EDX, EBP, ESI and EDI are referred to as general purpose registers.

The base architecture also includes six directly accessible segments, each up to 4 Gbytes in size.
The segments are indicated by the selector values placed in Intel386 DX segment registers of (slide 240) Various selector values can be loaded as a program executes, if desired.

The selectors are also task-specific, so the segment registers are automatically loaded with new context upon a task switch operation. The other types of registers, Control, System Address, Debug, and Test, are primarily used by system software.

MICROPROCESSOR ARCHITECTURE REVATI M WAHUL

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