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SIS20:A CMOS ASIC for SOLAR IRRADIANCE SENSORS in MARS SURFACE

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Presentation on theme: "SIS20:A CMOS ASIC for SOLAR IRRADIANCE SENSORS in MARS SURFACE"— Presentation transcript:

1 SIS20:A CMOS ASIC for SOLAR IRRADIANCE SENSORS in MARS SURFACE
D. Vázquez, S. Espejo, J. Ceballos, A. Ragel, C. Aledo, L. Carranza, J.M. Mora, M.A. Lagos

2 INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS
OUTLINE INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS

3 INTRODUCCIÓN Meteorological instruments typically present in orbital devices, Rovers, probes, etc. Surface instruments complements information provided by orbital devices. In the context of Mars: Meteorological stations in the Surface are critical to understanding the climate and atmospheric dynamics. This work presents SIS20: A Mixed-Signal Front-End ASIC for a Solar Irradiance Sensor to be included in the METEO Package of the ExoMars2020 Mission. It has been conceived in collaboration with INTA (National Institute of Aerospacial Technologies, Spain)

4 INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS
OUTLINE INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS

5 ASIC SIS20: ASIC DESCRIPTION
BLOCK DIAGRAM SPI Interface Processing Blocks SRAM Memories and Registers Control circuitry Miscelaneous, etc CLK & POR Misc. Analog MUXs & Digital BUS TIA 1 TIA 2 TIA 10 . Trans-Impedance Amplifiers Instr. Amplifier & 16-Bits ADC Instr. Amp & ADC 10-Bits DAC (Subranging) 10-Bits subr. DAC . PCS 1 PCS 2 PCS 4 Program. Current Sources GATOs (References & Test signals) Global Analog Test Observ. 8-bits CS DAC 8-Bits Current Steering DAC BANDGAP Vs & Is References Voltage & Current Refs

6 ASIC SIS20: ASIC DESCRIPTION
BLOCK DIAGRAM SPI Interface Processing Blocks SRAM Memories and Registers Control circuitry Miscelaneous, etc CLK & POR Misc. Analog MUXs & Digital BUS TIA 1 TIA 2 TIA 10 . Instr. Amplifier & 16-Bits ADC 10-Bits DAC (Subranging) . PCS 1 PCS 2 PCS 4 GATOs (References & Test signals) BANDGAP Vs & Is References 8-bits CS DAC

7 SIS20: ASIC DESCRIPTION TIAs CHANNELS 1M/2pF RC High 100k/20pF RC Low
RC Networks for Low/High configuration modes TIAs CHANNELS 1M/2pF RC High 100k/20pF RC Low CMOS Switches for Offset meas & compensation Photo-Diode CMOS Switches for gain mode selection Pad 2-stage Folded Cascode OTA Chip 10 channels total: 9 Channels meas 1 Channel calibration. Shared Reference Bias (internal) but external accesing for shielding

8 SIS20: ASIC DESCRIPTION 16-bit (1-bit sign) ADC Channel and Input Multiplexer Dual Slope 50MHz On-chip Clock FSM DIGITAL CONTROL Differential Input Data Out gain Level-shift Start EoC PREAMP-1 PREAMP-2 INTEGR. COMPARATOR PREAMP-1: Capacitive input impedance Programmable gain 1/50 PREAMP-2: Unity gain Signal accomodation by level shifting CMOS MUX ADC TIAs PT1000 VREFs Internal Signals etc. Preamps can also be used as General purpose VGA.

9 SIS20: ASIC DESCRIPTION PCS Channels for Temperature Measurement
Based on Resistance dependence of PT1000 with temperature I to V conversion by a digitally controlled 4-bit resolution Current Source 4-bit resolution Programmable Current Source [0, 750mA] Internal Vref (0.3V) Ground (0V) 4 3 2 1 CHIP To ADC From Digital Control Common Node 4 Channels (PT1000)

10 SIS20: ASIC DESCRIPTION 10-bits Sub-ranging DAC
Topology based on a conventional resistive ladder structure + multiplexer Used to improve the resolution of the processed data Generates a 10-bit resolution voltaje reference [0; 2,5V] to be connected to the negative rail of the ADC channel. LSB -> 2,441mV

11 BANDGAP OPAMP Feedback Loop
SIS20: ASIC DESCRIPTION 10-bits Subranging DAC 8-bits Current Steering Output DAC Topology based on a conventional resistive ladder structure + multiplexer Off-chip led CS DAC DAC output Used to improve the resolution of the processed data Used for calibration and monitoring Range [0; 25.5mA] LSB -> 100uA Voltage & Current References Generates a 10-bit resolution voltaje reference [0; 2,5V] to be connected to the negative rail of the ADC channel. LSB -> 2,441mV VREF = 2.5V BANDGAP OPAMP Feedback Loop IREF= 100uA R External Low Temp Coeff Resistor ASIC Temperature (PTAT + Res.) & Power Supply (VDD divider) Indicators All Voltage & Current References are derived from VREF & IREF

12 SPI Communication Interface
Memories & Registers Processing & Control Miscellaneous (Test) Clock generator

13 INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS
OUTLINE INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS

14 Experimental Results 4mm 3.3V CMOS 0.35u RHBD (IMSE-RHBDLib) 68 pins
(I/O pins -> 5.0V) Operating conditions: -125ºC to 50ºC 5mm

15 Experimental Results TIA Channel in Low & High Gain Modes
After leakage current compensation The Slope represents the measured resistance Maximun opamps offset measured over 10 samples: 470mV -125ºC)

16 Experimental Results 16-bits ADC Chain
Values accumulated over 256 measurements Good behavior in terms of linearity and noise, but gain and offset errors need to be compensated by Earth.

17 Experimental Results Programmable Voltage Reference [0; 2.5V] through the 10-bit DAC [0;25.5mA] 10-bit Current Steering DAC Global Voltage Reference from Bandgap behavior vs Temperature Max. Variation = ±21ppm/ºC Mean = 2.48V Standard Dev.= 0.45%

18 INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS
OUTLINE INTRODUCTION ASIC DESCRIPTION EXPERIMENTAL RESULTS CONCLUSIONS

19 Conclusions A Mixed-Signal ASIC (SIS20) in a standard CMOS 0.35mm technology has been presented. It is a Front-End for a Solar Irradiance Sensor on the surface of Mars. (METEO package in the ExoMars2020 mission). RHBD techniques have been applied and use the Rad-Hard Library developed at the Institute of Microelectronics of Seville (IMSE). The ASIC and main block’s functionality have been briefly described. The functional operation and technical specifications have been verified in the lab for the specified range of temperature (-125ºC to 50ºC). The qualification of the ASIC is still pending. However, it is expected to be satisfactory attending previous experiences on ASICs of the same characteristics and designed in the same technology using RHDB techniques and the same Rad-Hard library.


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