Presentation is loading. Please wait.

Presentation is loading. Please wait.

Reinventing The Wheel: Developing a New Standard-Cell Synthesis Flow

Published byĐào Văn Modified over 5 years ago

Similar presentations

Presentation on theme: "Reinventing The Wheel: Developing a New Standard-Cell Synthesis Flow"— Presentation transcript:

1 Reinventing The Wheel: Developing a New Standard-Cell Synthesis Flow
Alan Mishchenko University of California, Berkeley

2 Outline Motivation The flow Experimental results Conclusion
Technology-independent synthesis Technology mapping Buffering Sizing Experimental results Conclusion

3 Motivation Synthesis tools are out there, but they are
slow suboptimal complicated expensive It would be nice to speed them up improve their quality simplify them and make them free (like ABC) 

4 The Flow Technology-independent synthesis Technology mapping Buffering
Sizing These steps are not disconnected; they overlap Synthesis talks to mapping through structural choices Mapping talks to buffering through fanout estimations Buffer and sizing can be interleaved

5 Synthesis: Old and New “AIG rewriting” Delay/area costs Restructuring
AND2 levels/nodes Restructuring for all 4-input cuts, try all AIG subgraphs, choose the one with the min nodes under delay constraint Results Acceptable quality Acceptable runtime Problems “Over-re-structuring” Slow for large, deep logic “AIG reshaping” Delay/area cost user-specified cost for n-input AND/XOR/MUX/MAJ Restructuring iterate “mapping” and “unmapping” several times Results Comparable quality 3-10 faster Problems None so far

6 Mapping: Old and New “Traditional” cut-based mapping
iterate over the subject graph re-compute priority cuts use structural or functional matching (ICCAD’97) For standard-cell mapping use a gain-based library map both (pos and neg) phase of each node into gates select best cuts (gates) Results Acceptable quality Tolerable runtime “Improved” cut-based mapping pre-compute priority cuts iterate over the subject graph evaluate cuts using different costs use structural or functional matching For standard-cell mapping use a gain-based library map into NPN classes of functions from the library select best cuts (NPN classes) perform phase-assignment and determine gates during buffering Results Quality not known yet Runtime is expected 3-10x faster

7 Buffering: Old and New Several ideas tried, none is a clear winner
Enumerating buffer tree topologies Buffering for near-continuous libraries Other incremental local fanout optimization methods Several ideas tried, none is a clear winner “Technology-independent” buffering after the gain-based library Buffer-tree construction given required times and loads of the fanouts Incremental buffering interleaved with incremental sizing Results are mixed

8 Incremental Buffering Illustrated
Growing Bypassing

9 Sizing: Old and New Non-linear programming Linear programming
Lagrangian multipliers Incremental sizing find critical region find best gates to resize perform the resizing incrementally update timing Iterate until no improvement Can be combined with incremental buffering Results Reasonable Surprisingly fast If an optimum solution exists, seems to converge

10 Commands of The Flow read_lib write_lib print_lib read_scl write_scl
dump_genlib print_gs stime buffer unbuffer minsize maxsize upsize dnsize print_buf read_constr print_constr reset_constr

11 Experimental Setting 19 OpenCore designs were synthesized and mapped by an industrial tool using public library vsclib013.lib from Delay, area, and runtime were collected and used as a reference Sizing was tested by applying min-sizing, followed by re-sizing Buffering was tested by un-buffering and min-sizing, followed by re-buffering and re-sizing The flow was tested by restructuring the design, followed by mapping, buffering, and sizing

12 Experimental Results

13 Comments Column “Gate” shows the number of gates produced by the industrial tool Other columns “Gate” show the percentage of change in the number of gates after reach transform, compared to the result produced by the industrial too. Positive is improvement. Negative is degradation. Similarly, columns “Area” and “Delay” show the percentage of change in area and delay, respectively. The flows are tuned differently This is why the area increase after buffering/sizing is more than after synthesis/buffering/sizing. Runtimes are in seconds on an old desktop computer On a new computer, the runtimes are expected to be 2x smaller

14 Potential Issues Not specifying input driving cells and output loads
This was addressed but not yet experimented with Over-tuning for one particular library Not sure heuristics will hold for submicron libraries Not looking at power Not taking high and low Vt cells into account

15 Conclusion A new synthesis flow is being developed and implemented in ABC An opportunity to rethink some of the classical problems improve on some of the known solutions come up with a new public implementation Results are still inconclusive area (in area-oriented synthesis) is good (not shown) delay (in delay-oriented synthesis) is about 15% off runtime is about 20-50x better

16 Abstract This presentation focuses on adding new capabilities to synthesize standard cell designs in the public-domain synthesis/verification tool ABC. An optimization flow has been developed, which included gain-based technology mapping, fanout-optimization by buffering and gate duplication, and gate-sizing. Novel heuristic algorithms have been proposed for several well-known optimization steps. For example, buffer tree construction can be performed not as a separate step, but concurrently with gate-sizing by reshaping initial well-balanced buffer trees. Each tree reshaping and each gate resizing transform are evaluated for delay/area improvement using a common cost-function and the most promising one is selected. The delay is measured by lookup table based delay model, which computes the delay of a gate from its input flew and output capacitance. Experiments show that the flow produces results that are 10% within those of industrial tools 20x faster.

Download ppt "Reinventing The Wheel: Developing a New Standard-Cell Synthesis Flow"

Similar presentations

ECE 667 Synthesis and Verification of Digital Systems

ECE 667 Synthesis and Verification of Digital Systems
Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.

Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.
Power-Aware Placement

Power-Aware Placement
DAG-Aware AIG Rewriting Alan Mishchenko, Satrajit Chatterjee, Robert Brayton Department of EECS, University of California Berkeley Presented by Rozana.

DAG-Aware AIG Rewriting Alan Mishchenko, Satrajit Chatterjee, Robert Brayton Department of EECS, University of California Berkeley Presented by Rozana.
1 A New Enhanced Approach to Technology Mapping Alan Mishchenko Presented by: Sheng Xu May 2 nd 2006.

1 A New Enhanced Approach to Technology Mapping Alan Mishchenko Presented by: Sheng Xu May 2 nd 2006.
Reinventing The Wheel: Developing a New Standard-Cell Synthesis Flow Alan Mishchenko University of California, Berkeley.

Reinventing The Wheel: Developing a New Standard-Cell Synthesis Flow Alan Mishchenko University of California, Berkeley.
Logic Synthesis Primer

Logic Synthesis Primer
Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich VLSI CAD Lab Computer Science Department University of California,

Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich VLSI CAD Lab Computer Science Department University of California,
1 A Method for Fast Delay/Area Estimation EE219b Semester Project Mike Sheets May 16, 2000.

1 A Method for Fast Delay/Area Estimation EE219b Semester Project Mike Sheets May 16, 2000.
Electrical and Computer Engineering Archana Rengaraj ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011.

Electrical and Computer Engineering Archana Rengaraj ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011.
A NEW ECO TECHNOLOGY FOR FUNCTIONAL CHANGES AND REMOVING TIMING VIOLATIONS Jui-Hung Hung, Yao-Kai Yeh,Yung-Sheng Tseng and Tsai-Ming Hsieh Dept. of Information.

A NEW ECO TECHNOLOGY FOR FUNCTIONAL CHANGES AND REMOVING TIMING VIOLATIONS Jui-Hung Hung, Yao-Kai Yeh,Yung-Sheng Tseng and Tsai-Ming Hsieh Dept. of Information.
05/04/06 1 Integrating Logic Synthesis, Tech mapping and Retiming Presented by Atchuthan Perinkulam Based on the above paper by A. Mishchenko et al, UCAL.

05/04/06 1 Integrating Logic Synthesis, Tech mapping and Retiming Presented by Atchuthan Perinkulam Based on the above paper by A. Mishchenko et al, UCAL.
1 EECS 219B Spring 2001 Timing Optimization Andreas Kuehlmann.

1 EECS 219B Spring 2001 Timing Optimization Andreas Kuehlmann.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Combinational network delay. n Logic optimization.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Combinational network delay. n Logic optimization.
Combinational and Sequential Mapping with Priority Cuts Alan Mishchenko Sungmin Cho Satrajit Chatterjee Robert Brayton UC Berkeley.

Combinational and Sequential Mapping with Priority Cuts Alan Mishchenko Sungmin Cho Satrajit Chatterjee Robert Brayton UC Berkeley.
ABC: A System for Sequential Synthesis and Verification BVSRC Berkeley Verification and Synthesis Research Center Robert Brayton, Niklas Een, Alan Mishchenko,

ABC: A System for Sequential Synthesis and Verification BVSRC Berkeley Verification and Synthesis Research Center Robert Brayton, Niklas Een, Alan Mishchenko,
Wenlong Yang Lingli Wang State Key Lab of ASIC and System Fudan University, Shanghai, China Alan Mishchenko Department of EECS University of California,

Wenlong Yang Lingli Wang State Key Lab of ASIC and System Fudan University, Shanghai, China Alan Mishchenko Department of EECS University of California,
Logic synthesis flow Technology independent mapping –Two level or multilevel optimization to optimize a coarse metric related to area/delay Technology.

Logic synthesis flow Technology independent mapping –Two level or multilevel optimization to optimize a coarse metric related to area/delay Technology.
Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Combinational network delay. n Logic optimization.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Combinational network delay. n Logic optimization.
In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He Electrical Engineering Dept., UCLA Presented by Ju-Yueh Lee Address comments.

In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He Electrical Engineering Dept., UCLA Presented by Ju-Yueh Lee Address comments.

Similar presentations

Ads by Google