1. November 12, 2003 1 Instrument Electronics Henrik von der Lippe Lawrence Berkeley National Laboratory November 11 th, 2003

2. November 12, 2003 2 Overview & strategy Baseline for SNAP Instrument electronics system R&D goals Progress last year CCD & IR focal plane modules Mass memory & Compression Observatory Control Unit Schedule Manpower R&D management R&D deliverables Summary Outline

3. November 12, 2003 3 Instrument electronics OCU & Mem Spectrograph Imager Star Guider Thermal Ctrl

4. November 12, 2003 4 Instrument Electronics Layout Focal plane Mass memory OCU Power system Battery

5. November 12, 2003 5 Strategy for Instrument Electronics Employ existing, tested solutions with space flight heritage wherever possible Avoid single-point failures and maintain redundancy where possible within power, weight, cost budgets Keep number of components and interconnections to a minimum for reliability Reduce number and length of cables carrying low-level analog signals to avoid noise pickup, crosstalk Use a common architecture for readout of different sensors to extent possible, to reduce number of different electronics systems Have a fallback option for areas of technical or schedule risk

6. November 12, 2003 6 Baseline SNAP Electrical System System is has no single point failures —Fully redundant and cross strapped on spacecraft side —Redundant Observatory Control Units and Large Memories on instrument side —Instrument Detectors and Mechanisms modularized for failure tolerance Uses Industry Standard (e.g. 1553) interface between instrument and spacecraft Wide band downlink controlled directly by instrument Memory Capability incorporated into the Instrument —No need for Solid State Recorder in spacecraft Spacecraft consists of 3 independent modules connected by a 1553 bus —Power system —ACS System —C&DH System

7. November 12, 2003 7 R&D Goals 1.Risk mitigation through early R&D 2.System requirements & interface control documents 3.Conceptual design of electronics/DAQ system/Instrument control 4.Realistic cost & schedule estimate for CDR There are only a few key areas where hands-on R&D is required for risk mitigation, mostly in front-end readout and control The remainder of the electronics R&D program consists primarily of requirements & interface documentation, conceptual design studies, and cost and schedule estimates for the CDR.

8. November 12, 2003 8 Electronics Working Concept Front-end electronics (control and readout) mounted on back of cold plate +Reduces cable plant, simplifies grounding & shielding issues, mass +Minimize cross-talk, pickup for small analog signals +Reduces power consumption due to increase in e- mobility +Avoid problems associated with driver on CCD - power, noise +Compatible with HgCdTe readout being developed by Rockwell for NASA - must be <10 cm from sensor & operate cold –Thermal constraints - must keep cold plate cold –Implications for total power and mass of cold plate Back-end electronics located in shielded room temperature boxes mounted on space craft +Lower radiation exposure +Simpler temperature requirement +No thermal impact on focal plane

9. November 12, 2003 9 Progress last year Successful Front-end test IC (CRIC) Design specs: — Photometry: CCD + electronic noise  4.0e- rms — Spectrograph: CCD + electronic noise  2.0e- rms — Large dynamic range: 96dB from noise floor to 130k e- well depth (16-bit) — Readout frequency: 100 kHz & 50kHz — Radiation tolerance: 10 kRad ionization (well shielded) — Power:  200mJ/image/channel => 10mW/channel (6.5mW for the analog front-end, 3.5mW for the ADC) — Operation at 140K and 300K Combined CRIC-CCD test in progress (one year ahead of schedule) Radiation tolerance testing in progress Overall block diagram for the instrument has been developed

10. November 12, 2003 10 CCD module Star Guider CRIC ASIC – Dual-ramp correlated Double Sampler with a multislope integrator for each corner of the CCD. 96 dB dynamic range ADC – 12-bit, 100 kHz equivalent conversion rate per CCD Backup FE under development by Paris-VI Sequencer – Clock pattern generator supporting modes of operation: erase, expose, readout, idle. Clock drivers – Programmable amplitude and rise/fall times. Voltages ~20V Bias and power generation – Provide switched, programmable large voltages for CCD and local power. (60-80V) Temperature monitoring – Local and remote. DAQ and instrument control interface – Path to data buffer memory, master timing, and configuration and control.

11. November 12, 2003 11 IR module Bias and power generation – Provide bias voltages for detector & multiplexer Temperature monitoring DAQ and instrument control interface – Path to data buffer memory, master timing, and configuration and control. The Rockwell SIDECAR ASIC provides: — Programmable gain pre-amplification — 16 bit, 100kHz Analog to digital conversion Sequencer – Clock pattern generator supporting modes of operation: erase, expose, readout, idle. Control signals for reading out the mux Multi-read averaging for noise reduction

12. November 12, 2003 12 Observatory Control Unit (OCU) Includes all interfaces to the detectors and instrument for both science and housekeeping data — A given unit connects to either the prime or the redundant interface on focal plane modules Has redundant cross strapped interface to Spacecraft Electronics Comprised of seven major subassemblies — DPU Interfaces to SC C&DH via a single 1553 port on the DPU Provides command and engineering data interface — Memory Control / Formatter Manages Instrument data storage memory Provides 300 Mhz science data output which directly drives the Ka band transmitter — Data Compression Lossless compression of all science data — I/O and Control Collect focal plane science data Operates motors and mechanisms Collects instrument housekeeping Performs power distribution to focal plane electronics Centroid calculation of guider star for the ACS — Calibration control Controls all calibration lamps — Thermal control Sets up control for ~1k heater elements — Power Control

13. November 12, 2003 13 Mass memory Two memory technology types are being studied —Flash —DRAM Tests: 1. Error rate 2. Access speed 3. Durability (# write cycles) 4. Radiation tolerance Total dose SEU SEL

14. November 12, 2003 14 Data Compression Algorithms — CCSDS 120.0 Baseline (Rice) — Sqrt(N) + CCSDS 120.0 — The algorithms are being test with data from SLOAN and GOODS Evaluation of FPGA for algorithm implementation — Survey of alternative FPGA’s — Performance — Radiation Tests on Candidate FPGA Technologies Evaluation of ASIC’s — Survey of existing IC’s — Applicability of existing IC to SNAP

15. November 12, 2003 15 R&D Schedule Milestones

16. November 12, 2003 16 R&D Schedule Milestones

17. November 12, 2003 17 R&D Schedule Milestones

18. November 12, 2003 18 R&D Schedule Milestones

19. November 12, 2003 19 R&D Schedule Milestones

20. November 12, 2003 20 Manpower LBNLCALTECHPARIS XI A. Karcher H. von der Lippe J-P. Walder G. Zizka R. Smith M. Bonati D. Guzman E. Barlett J-F. Genat H. Lebollo R. Sefri FNAL (pending) SLAC (pending) W. Wester (MM) C. Nelson (MM) G. Cardoso (Comp) G. Cancelo (Comp) W. Althouse M. E. Huffer New hire

21. November 12, 2003 21 Electronics R&D Management Team lead is H. von der Lippe (LBNL) Weekly meetings with scientists & engineers to review progress, discuss requirements, etc. Bi-weekly video meetings between LBNL and Paris to coordinate electronic R&D activities. These meeting will be converted to Instrument Electronics meetings Regular participation in SNAP science, CCD detector, SNAP system engineering & management meetings Instrument manager meetings to coordinate between electronics R&D and CCD, HgCdTe, spectrograph R&D activities Planning for internal and external reviews — Preliminary design requirements review — Pre-submission IC design, simulation & verification review — Preliminary conceptual design review

22. November 12, 2003 22 R&D Deliverables Two classes Paper trade studies and conceptual design studies Active SNAP advancement of a technology “Paper” deliverables Detailed requirements & interface control documents Overall system architecture & design partitioning Power, grounding & shielding plan Study of CCD controller options: FPGA, commercial part, VHDL (Custom IC) Study of memory components Study of compression algorithms Study of thermal control system Plan for space-qualification of all parts Hardware deliverables CCD front-end test chip; irradiation & low-temp testing Test of Rockwell HgCdTe readout IC (SIDECAR) Prototype demonstration for front-end readout: - CDS/ADC + CCD sensor - HgCdTe readout + sensor

23. November 12, 2003 23 Summary SNAP instrument electronics presents challenges for high channel count, low noise, low power, low temperature, large dynamic range, and radiation tolerance R&D phase will be used to develop requirements, interfaces and system architecture as basis for a detailed cost and schedule for the Conceptual Design Report Development of ASIC-based front-end readout requires a limited and focused plan for hands-on R&D towards proof-of- principle prototypes R&D management is in place and already actively guiding development