1. ©Brooks/Cole, 2003 Chapter 5 Computer Organization

2. ©Brooks/Cole, 2003 Figure 5-1 Computer hardware (subsystems)

3. ©Brooks/Cole, 2003 CENTRALPROCESSING UNIT (CPU) CENTRALPROCESSING 5.1

4. ©Brooks/Cole, 2003 Figure 5-2 Central Processing Unit 1.Arithmetic Logical Unit (ALU) 2.Registers 3.Control Unit

5. ©Brooks/Cole, 2003 Arithmetic Logical Unit (ALU) ALU performs arithmetic and logical operation Arithmetic Operation (increment, decrement, add, subtract….) Logical Operation (NOT, AND, OR, XOR..) Control Unit is responsible for selecting one of the logical and arithmetic operation

6. ©Brooks/Cole, 2003 Registers Registers are fast storage locations that hold data temporarily There are three types of registers; –Data Registers: used to hold input data to be processed in ALU and the results. –Instruction Registers: used to hold program instruction from the memory. –Program Counter: used to keep track of the instruction currently being executed, after execution of the counter incremented to point to the next instruction

7. ©Brooks/Cole, 2003 MAIN MEMORY 5.2

8. ©Brooks/Cole, 2003 Main Memory Main memory is a collection of storage locations, each with a unique address. Data are transferred to and from memory in groups of bits called words. A word can be 8 bits (byte), 16 bits (2-byte), 32 bits (4-byte) and 64 bits (8 byte).

9. ©Brooks/Cole, 2003 Table 5.1 Memory units Unit Unit ------------ kilobyte megabyte gigabyte terabyte petabyte exabyte Approximation Approximation ------------ 10 3 bytes 10 6 bytes 10 9 bytes 10 12 bytes 10 15 bytes 10 18 bytes Exact Number of bytes Exact Number of bytes ------------------------ 2 10 (1024) bytes 2 20 (1,048,576) bytes 2 30 (1,073,741,824)bytes 2 40 bytes 2 50 bytes 2 60 bytes

10. ©Brooks/Cole, 2003 Address Space Each word in a memory has a unique identifier (address) For example, a memory with 64 kilobyte and a word of 1 byte has address space that range from 0 to 65353.

11. ©Brooks/Cole, 2003 Figure 5-3 Main memory

12. ©Brooks/Cole, 2003 Address as bit pattern Address is stored as bit patterns Each word in the memory has a unique address An address is a unsigned number stored as an unsigned integer The number of addresses’ bit patterns is equal to the number of words in the memory If computer has N number of words of memory, the number of bits in an address bit pattern is giving by Log 2 N = 3.2 Log 10 N

13. ©Brooks/Cole, 2003 Example 1 A computer has 32 MB (megabytes) of memory. How many bits are needed to address any single byte in memory? Solution

14. ©Brooks/Cole, 2003 Example 2 A computer has 128 MB of memory. Each word in this computer is 8 bytes. How many bits are needed to address any single word in memory? Solution

15. ©Brooks/Cole, 2003 Memory Types Memory are two types: –Random Access Memory (RAM) –Read Only Memory (ROM)

16. ©Brooks/Cole, 2003 Random Access Memory (RAM) Makes most of the main memory A user can read and write from and to the RAM. It is erasable (user can erase written data) It is volatile (information is deleted if power is down)

17. ©Brooks/Cole, 2003 RAM Technology RAM Technology is divided into: 1.Static RAM (SRAM): uses flip-flop (a logic electronic device) to hold bit state as long as power is on. It doesn't need refreshing. It is fast and expensive. 2.Dynamic RAM (DRAM): uses capacitor (an eclectic device) to hold bit state. When capacitor is charged, state is 1 and when capacitor is uncharged, state is 0. it needs refreshing. It is slow and inexpensive.

18. ©Brooks/Cole, 2003 Read Only Memory The data in the ROM is written by the computer manufacturer User is only allowed to read from the ROM, not to write. Nonvolatile (data are not erased when power is off) Used to hold booting program that runs when you switch on the computer.

19. ©Brooks/Cole, 2003 ROM Technology Programmable ROM (PROM): user can store programs in PROM. Once stored, programs can not be erased. Erasable Programmable ROM (EPROM): user can program it. It is only erased by special device. Electronically EPROM (EEPROM): user can erase programs using electronic impulse.

20. ©Brooks/Cole, 2003 Memory Hierarchy Computer users need a lot of memory. Cheap memory is not very fast Fast memory is not cheap. A compromise needed to be made. The solution is hierarchical levels of memory.

21. ©Brooks/Cole, 2003 Figure 5-4 Memory hierarchy Use small amount of high speed memory, when speed is important, use registers inside the CPU. Use moderate amount of medium speed memory to store data that accessed often. Use large amount of low speed memory data that are not often accessed.

22. ©Brooks/Cole, 2003 Figure 5-5 Cache Cache memory is faster than main memory but slower than the CPU and registers inside the CPU. Cache is placed between the CPU and main memory

23. ©Brooks/Cole, 2003 Cache Memory When CPU needs to access a word, the procedure is: 1.CPU check the cache. 2.If the word is there it copies it, if not, CPU access the main memory and copies a block of memory starting with the desired word. This block replaces the data in the cache memory. 3.CPU accesses the cache and copies the word.

24. ©Brooks/Cole, 2003 80-20 rule Q: How cache is efficient despite small size? A: Most computer spend 80% of time accessing 20% of the data in the memory. These data are accessed over and over again. Cache memory which is fast speed can hold this 20% of data to make fast access to data at least 80% of time.

25. ©Brooks/Cole, 2003 INPUT / OUTPUT 5.3

26. ©Brooks/Cole, 2003 Figure 5-6 Physical layout of a magnetic disk

27. ©Brooks/Cole, 2003 Figure 5-7 Surface organization of a disk

28. ©Brooks/Cole, 2003 Figure 5-8 Mechanical configuration of a tape

29. ©Brooks/Cole, 2003 Figure 5-9 Surface organization of a tape

30. ©Brooks/Cole, 2003 Figure 5-10 Creation and use of CD-ROM

31. ©Brooks/Cole, 2003 Table 5.2 CD-ROM speeds Speed ------------ 1x 2x 4x 6x 8x 12x 16x 24x 32x 40x Data Rate Data Rate ------------------------ 153,600 bytes per second 307,200 bytes per second 614,400 bytes per second 921,600 bytes per second 1,228,800 bytes per second 1,843,200 bytes per second 2,457,600 bytes per second 3,688,400 bytes per second 4,915,200 bytes per second 6,144,000 bytes per second Approximation Approximation ------------ 150 KB/s 300 KB/s 600 KB/s 900 KB/s 1.2 MB/s 1.8 MB/s 2.4 MB/s 3.6 MB/s 4.8 MB/s 6 MB/s

32. ©Brooks/Cole, 2003 Figure 5-11 CD-ROM format

33. ©Brooks/Cole, 2003 Figure 5-12 Making a CD-R

34. ©Brooks/Cole, 2003 Figure 5-13 Making a CD-RW

35. ©Brooks/Cole, 2003 Table 5.3 DVD capacities Feature Feature --------------------------------- single-sided, single-layer single-sided, dual-layer double-sided, single-layer double-sided, dual-layer Capacity Capacity ------------ 4.7 GB 8.5 GB 9.4 GB 17 GB

36. ©Brooks/Cole, 2003 SUBSYSTEMINTERCONNECTIONSUBSYSTEMINTERCONNECTION 5.4

37. Figure 5-14 Connecting CPU and memory using three buses

38. ©Brooks/Cole, 2003 Figure 5-15 Connecting I/O devices to the buses

39. ©Brooks/Cole, 2003 Figure 5-16 SCSI controller

40. ©Brooks/Cole, 2003 Figure 5-17 FireWire controller

41. ©Brooks/Cole, 2003 Figure 5-18 USB controller

42. ©Brooks/Cole, 2003 Figure 5-19 Isolated I/O addressing

43. ©Brooks/Cole, 2003 Figure 5-20 Memory-mapped I/O addressing

44. ©Brooks/Cole, 2003 PROGRAMEXECUTIONPROGRAMEXECUTION 5.5

45. Figure 5-21 Steps of a cycle

46. ©Brooks/Cole, 2003 Figure 5-22 Contents of memory and register before execution

47. ©Brooks/Cole, 2003 Figure 5-23.a Contents of memory and registers after each cycle

48. ©Brooks/Cole, 2003 Figure 5-23.b Contents of memory and registers after each cycle

49. ©Brooks/Cole, 2003 Figure 5-23.c Contents of memory and registers after each cycle

50. ©Brooks/Cole, 2003 Figure 5-23.d Contents of memory and registers after each cycle

51. ©Brooks/Cole, 2003 Figure 5-24 Programmed I/O

52. ©Brooks/Cole, 2003 Figure 5-25 Interrupt-driven I/O

53. ©Brooks/Cole, 2003 Figure 5-26 DMA connection to the general bus

54. ©Brooks/Cole, 2003 Figure 5-27 DMA input/output

55. ©Brooks/Cole, 2003 TWO DIFFERENT ARCHITECTURES ARCHITECTURES 5.6