1. Click the LH mouse button to begin the animation
CMOS Inverter Layout
Click the LH mouse button to begin the animation
Input
Output
Vdd
n-well
well tap
substrate tap
Vss

2. CMOS Inverter Structure
n-well
Vss
Input
Output
Vdd
substrate tap
well tap
field oxide
n-well
p-substrate
metal p+
polysilicon
gate oxide n+

3. CMOS Inverter Structure
n-well
Vss
Input
Output
Vdd
substrate tap
well tap
field oxide
n-well
p-substrate
metal p+
polysilicon
gate oxide n+

4. Polysilicon Design Rule
Click the LH mouse button to begin the animation

5. Polysilicon Design Rule
Input
Output
No overlap of channel. Insufficient overlap of cut.

6. Polysilicon Design Rule
Input
Output
Faulty m1-p connection
Current not controlled by gate
Current not controlled by gate

7. Polysilicon Design Rule
Input
Output
Adequate overlap of channel. Sufficient overlap of cut.

8. Polysilicon Design Rule
Input
Output