Presentation is loading. Please wait.

Presentation is loading. Please wait.

Elec 2607 Digital Switching Circuits

Published byYenny Kusnadi Modified over 5 years ago

Similar presentations

Presentation on theme: "Elec 2607 Digital Switching Circuits"— Presentation transcript:

1 Elec 2607 Digital Switching Circuits
Lecture 13 & 14: Digital Logic 26/12/2018 ELEC 2607 Lecture 13 & 14:

2 26/12/2018 ELEC 2607 Lecture 0:

3 ANOTHER FORM OF Digital Logic
26/12/2018 ELEC 2607 Lecture 13 & 14:

4 X Consider X = 0 Then change X = 1 26/12/2018
ELEC 2607 Lecture 13 & 14:

5 26/12/2018 ELEC 2607 Lecture 13 & 14:

6 Extra 1

7 Decoder from binary to octal
Timing problems Glitches reason hidden inside chip Extra 2 26/12/2018 ELEC 2607 Lecture 13 & 14:

8 Extra 3 26/12/2018 ELEC 2607 Lecture 13 & 14:
FIGURE Decoder waveform displays showing how transitional input states produce glitches in the output waveforms. Extra 3 26/12/2018 ELEC 2607 Lecture 13 & 14:

9 Decoder from binary to octal
Application of a strobe waveform to eliminate glitches on decoder outputs. Chip is active only when outputs are stable. Decoder from binary to octal Extra 4 26/12/2018 ELEC 2607 Lecture 13 & 14:

10 Have a better way to do this analysis
Output = XX Have a better way to do this analysis 26/12/2018 ELEC 2607 Lecture 13 & 14:

11 Consider X = 1 Then change X = 0 Output = X + X 26/12/2018
ELEC 2607 Lecture 13 & 14:

12 Don’t do simplification on output functions.
Output = X(X + X) Don’t do simplification on output functions. Simplification changes the circuit Output = X +(X X) 26/12/2018 ELEC 2607 Lecture 13 & 14:

13 Can you make a proper timing diagram?
recover 1 1 1 time X = 1 Change X = 0 Can you make a proper timing diagram? 26/12/2018 ELEC 2607 Lecture 13 & 14:

14 26/12/2018 ELEC 2607 Lecture 13 & 14:

15 Two terms in expression ORed together Two loops in KMap
Sum of product form Two terms in expression ORed together Two loops in KMap 26/12/2018 ELEC 2607 Lecture 13 & 14:

16 Also Consider A = 0, B = 0 A = 1, B = 0 A = 0, B = 1
Consider again A=1 B =1 26/12/2018 ELEC 2607 Lecture 13 & 14:

17 26/12/2018 ELEC 2607 Lecture 13 & 14:

18 (complement = ‘) Wrong colors in map Extra examples on this required
26/12/2018 ELEC 2607 Lecture 13 & 14:

19 26/12/2018 ELEC 2607 Lecture 13 & 14:

20 26/12/2018 ELEC 2607 Lecture 13 & 14:

21 26/12/2018 ELEC 2607 Lecture 13 & 14:

22 See slide 12 and extra notes Circuits are only representative
For DYNAMICS See slide 12 and extra notes Circuits are only representative They need the delays in lower path Delays in lower path do not change output expression 26/12/2018 ELEC 2607 Lecture 13 & 14:

23 Applying simplification rules or expanding the function
CHANGES THE CIRCUIT Be careful 26/12/2018 ELEC 2607 Lecture 13 & 14:

24 Applying DeMorgan’s Law
IS OK 26/12/2018 ELEC 2607 Lecture 13 & 14:

25 26/12/2018 ELEC 2607 Lecture 13 & 14:

26 26/12/2018 ELEC 2607 Lecture 13 & 14:

27 26/12/2018 ELEC 2607 Lecture 13 & 14:

28 26/12/2018 ELEC 2607 Lecture 13 & 14:

29 26/12/2018 ELEC 2607 Lecture 13 & 14:

30 26/12/2018 ELEC 2607 Lecture 13 & 14:

31 Good place to take a break
Good place to start up again 26/12/2018 ELEC 2607 Lecture 13 & 14:

32 26/12/2018 ELEC 2607 Lecture 13 & 14:

33 26/12/2018 ELEC 2607 Lecture 13 & 14:

34 26/12/2018 ELEC 2607 Lecture 13 & 14:

35 26/12/2018 ELEC 2607 Lecture 13 & 14:

36 26/12/2018 ELEC 2607 Lecture 13 & 14:

37 26/12/2018 ELEC 2607 Lecture 13 & 14:

38 26/12/2018 ELEC 2607 Lecture 13 & 14:

39 Error: Should be 0 26/12/2018 ELEC 2607 Lecture 13 & 14:

40 26/12/2018 ELEC 2607 Lecture 13 & 14:

41 26/12/2018 ELEC 2607 Lecture 13 & 14:

42 26/12/2018 ELEC 2607 Lecture 13 & 14:

43 26/12/2018 ELEC 2607 Lecture 13 & 14:

44 26/12/2018 ELEC 2607 Lecture 13 & 14:

45 26/12/2018 ELEC 2607 Lecture 13 & 14:

46 26/12/2018 ELEC 2607 Lecture 13 & 14:

47 26/12/2018 ELEC 2607 Lecture 13 & 14:

48 26/12/2018 ELEC 2607 Lecture 13 & 14:

49 26/12/2018 ELEC 2607 Lecture 13 & 14:

50 26/12/2018 ELEC 2607 Lecture 13 & 14:

51 26/12/2018 ELEC 2607 Lecture 13 & 14:

52 26/12/2018 ELEC 2607 Lecture 13 & 14:

53 26/12/2018 ELEC 2607 Lecture 13 & 14:

54 26/12/2018 ELEC 2607 Lecture 13 & 14:

55 26/12/2018 ELEC 2607 Lecture 13 & 14:

56 26/12/2018 ELEC 2607 Lecture 13 & 14:

57 26/12/2018 ELEC 2607 Lecture 13 & 14:

58 26/12/2018 ELEC 2607 Lecture 13 & 14:

59 26/12/2018 ELEC 2607 Lecture 13 & 14:

60 26/12/2018 ELEC 2607 Lecture 13 & 14:

61 26/12/2018 ELEC 2607 Lecture 13 & 14:

Download ppt "Elec 2607 Digital Switching Circuits"

Similar presentations

CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.

CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.
Combinational Circuits

Combinational Circuits
ECE 3110: Introduction to Digital Systems

ECE 3110: Introduction to Digital Systems
K-Maps, Timing Sequential Circuits: Latches & Flip-Flops Lecture 4 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier,

K-Maps, Timing Sequential Circuits: Latches & Flip-Flops Lecture 4 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier,
1 Combinational Logic Network design Chapter 4 (continued ….)

1 Combinational Logic Network design Chapter 4 (continued ….)
1 Homework Reading –Tokheim, Section 5-10, 7-4 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.

1 Homework Reading –Tokheim, Section 5-10, 7-4 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.
EECC341 - Shaaban #1 Lec # 8 Winter 2001 1-9-2002 Combinational Logic Circuit Transient Vs. Steady-state Output Gate propagation delay: The time between.

EECC341 - Shaaban #1 Lec # 8 Winter Combinational Logic Circuit Transient Vs. Steady-state Output Gate propagation delay: The time between.
Give qualifications of instructors: DAP

Give qualifications of instructors: DAP
CS 151 Digital Systems Design Lecture 6 More Boolean Algebra A B.

CS 151 Digital Systems Design Lecture 6 More Boolean Algebra A B.
EE365 Adv. Digital Circuit Design Clarkson University Lecture #6

EE365 Adv. Digital Circuit Design Clarkson University Lecture #6
CHAPTER 3 Digital Logic Structures

CHAPTER 3 Digital Logic Structures
ECE C03 Lecture 61 Lecture 6 Delays and Timing in Multilevel Logic Synthesis Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.

ECE C03 Lecture 61 Lecture 6 Delays and Timing in Multilevel Logic Synthesis Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.

DIGITAL SYSTEMS TCE1111. 2 OTHER COMBINATIONAL LOGIC CIRCUITS DECODERS ENCODERS.

DIGITAL SYSTEMS TCE OTHER COMBINATIONAL LOGIC CIRCUITS DECODERS ENCODERS.
CS 151 Digital Systems Design Lecture 32 Hazards

CS 151 Digital Systems Design Lecture 32 Hazards
Boolean Algebra and Logic Simplification

Boolean Algebra and Logic Simplification
Digital Logic and Design Vishal Jethva Lecture No. 10 svbitec.wordpress.com.

Digital Logic and Design Vishal Jethva Lecture No. 10 svbitec.wordpress.com.
Logic Function Optimization. Combinational Logic Circuit Regular SOP and POS designs Do not care expressions Digital logic circuit applications Karnaugh.

Logic Function Optimization. Combinational Logic Circuit Regular SOP and POS designs Do not care expressions Digital logic circuit applications Karnaugh.
1 Digital Design: Time Behavior of Combinational Networks Credits : Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth,

1 Digital Design: Time Behavior of Combinational Networks Credits : Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth,
Apr. 3, 2000Systems Architecture I1 Systems Architecture I (CS 281-001) Lecture 3: Review of Digital Circuits and Logic Design Jeremy R. Johnson Mon. Apr.

Apr. 3, 2000Systems Architecture I1 Systems Architecture I (CS ) Lecture 3: Review of Digital Circuits and Logic Design Jeremy R. Johnson Mon. Apr.

Similar presentations

Ads by Google