1. Chap. 4: A Systematic Approach to Logic Design
Design of complex synchronous sequential digital circuits based on converting algorithmic descriptions into hardware
Uses a systematic step-by-step approach
FSM (Finite State Machine) method insufficient
Only suitable for small sequential circuits with small numbers of external inputs
Set of design heuristics for “safe” design
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2. Using Digital Circuits to Implement General Algorithms in Hardware
Formal definition of an “algorithm”
A general step-by-step procedure for solving a problem that is CORRECT and TERMINATES.
Informal definition of an “algorithm”
A computer-program-like procedure for solving the problem given.
Algorithm description methods
Old (outdated) method: flowchart
Pseudocode: free-form procedural description
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3. ASM (Algorithmic State Machine)
Originally introduced in 1973 by C. R. Clare
Example designs:
automatic bank tellers, soccer robot systems, computers
Advantages
Uses a systematic S/W-to-H/W conversion method
Can be used to design large circuits with many inputs
Disadvantages
Highly dependent on the use of a graphical notation called an ASM chart  cumbersome for large designs
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4. Introduction to Hardware Design
Classification of Design Methods
Top-down, bottom-up, combined
Design Level Hierarchy
architectural (CPUs, IOPs, memory modules, etc.)
register-transfer (registers, adders, counters, etc.)
gate (NAND, NOR, AND, flip-flops, etc.)
switch (view transistors as voltage-controlled switches)
transistor (lowest level used in circuit design)
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5. VLSI Chip Design versus Board-Level Design
VLSI Design (or ASIC Design)
Full-custom design
Draw patterns for each individual transistor and connection
Standard cell based design
Use a standard cell library (pre-design adder, counter, etc.) and automatic place-and-route tools
Board-Level Design
Produce acceptable design using available parts (chips)
PCB routing typically done by “PCB artwork” experts
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6. Design Method Differences
VLSI Chip Design
Uses PLAs, transistor-level-designed MSI devices
Uses latches and multi-phase clocks instead of FFs
Extremely short signal delays (within the chip)
Board-Level Design
Uses mostly standard, off-the-shelf (OTS) chips
Logic minimization less important than for chip design
Uses FFs and buffer (transceiver) chips
Uses PLDs and FPGAs extensively
Relatively long chip-to-chip signal delays
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7. Design Method Similarities
High-level design is the same
particularly for synchronous sequential circuits
ASM-based (modified ASM) high-level design methodology equally applicable to both
Heuristics for “safe” design should be followed for both VLSI chip design and board-level design
use of edge-triggered flip-flops is a possible exception
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8. Partitioning of Digital Circuits
Control Logic Section
logic required to generate control signals for registers, adders, counters, etc.
Datapath Section
all logic not included in the control logic section
typically the “word”-sized data manipulation and storage components through which the data “flows”
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9. "Computer Design" by Sunggu Lee
input data
control and
status signals
output
data
datapath
elements
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10. Structure of General Digital Circuit
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11. Register Transfer Notation (RTN)
Common notation for describing high-level behavior of digital systems
Fact: All (or almost all) synchronous sequential digital systems can be viewed as a set of registers and data transfer operations.
Operations in RTN are always of the form: REGx  f(REG1, REG2, … , REGn)
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12. "Computer Design" by Sunggu Lee
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13. "Computer Design" by Sunggu Lee
(Modified) ASM Method
(1) Pseudocode
create an algorithm to describe desired circuit operation
(2) ASM Chart
convert the pseudocode into an ASM chart
(3) Datapath
design the datapath based on the ASM chart
(4) Detailed ASM Chart
based on the ASM chart and datapath
(5) Control Logic Design
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14. "Computer Design" by Sunggu Lee
ASM Chart
A method for describing the sequential operations of a digital system
direct conversion from a computer algorithm
contains all information contained in a “state diagram”
Depiction of an ASM chart
original, graphical notation: similar to a “flowchart”
tabular notation possible
text notation possible
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15. Original ASM Chart Constructs
don’t
need
state box
condition box
conditional output
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16. ASM Chart Construction Rules
State boxes should contain only RTN statements
plus control signals (if necessary)
All operations within a state box must be executable in one clock cycle
Combine two state boxes if all operations in both state boxes can be executed in same clock cycle
Condition boxes should contain only simple “combinational logic” queries
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17. "Computer Design" by Sunggu Lee
Example 4.1: ASM Chart
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18. Tabular Form of ASM Chart
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19. "Computer Design" by Sunggu Lee
Text Form of ASM Chart
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20. "Computer Design" by Sunggu Lee
Datapath for Example 4.1
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21. "Computer Design" by Sunggu Lee
Detailed ASM Chart
One-to-one correspondence with ASM chart
RTN operation  list of control signals
unspecified control signals  default value of ‘0’
Condition box query  status signal
State box contains either
csig1, csig2, …, csigN
cond:(csig1, csig2, …, csigN)
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22. Detailed ASM Chart for Ex. 4.1
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23. Tabular Form of Detailed ASM Chart
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24. Text Form of Detailed ASM Chart
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25. "Computer Design" by Sunggu Lee
(Assume
C = FFH
initially)
FFH
(zeroC = 1
initially)
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26. Control Logic Design Methods
One-FF-per-state method
also referred to as “one-hot” or “delay element” method
MUX-based method
PLD-based method
results in the most compact implementation
Sequence-counter method
for use with cyclical state transition patterns
outputs of the “counter” are the control logic “states”
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27. One-FF-Per-State Method
Uses one-to-one transformations from detailed ASM chart constructs to digital logic components
State box transformation
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28. "Computer Design" by Sunggu Lee
Multiple-path transformation
Condition box transformation
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29. Example of Transformation Process
(D FF’s not
shown here)
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30. "Computer Design" by Sunggu Lee
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31. MUX-Based Control Logic Design
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33. "Computer Design" by Sunggu Lee
PLD-Based Approaches
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35. "Computer Design" by Sunggu Lee
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36. Overall (Modified) ASM Process
Write down a pseudocode solution
test it out using a short computer program
Convert the pseudocode to an ASM chart
try to “optimize” ASM chart, so it uses few states
Derive the datapath from the ASM chart
figure out the datapath components and signals needed
Form a detailed ASM Chart
Derive the control logic design
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37. ASM Design Example (Prob. 4.14)
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Solution Approach
Assume input voltage range is [0 , Vmax]
Use a binary approximation algorithm
Actual value
0 Volts
Vmax Volts
Guess 3
Guess 2
Guess 1
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39. Step 1: Possible Pseudocode Solution
While (true) do /* all H/W circuits run “infinitely” */ 1. done <- 0; 2. If (START) then done <- 0; i <- 7; output < ; /* binary value */ While (!done) do If (greater) then output<i> <- 1; else if (less) then output<i> <- 0; else /* equal */ done <- 1; If (i > 0) then i <- i - 1; else done <- 1; If (!done) then output<i> <- 1;
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41. "Computer Design" by Sunggu Lee
"Computer Design" by Sunggu Lee

42. Step 2: ASM Chart (Text Form)
s0: done  1;
c0: if (START) goto s1; else goto s0;
s1: done  0; i  7; output  80H;
s2:
c1: if (greater) goto s3; else if (less) goto s4;
s3: output<i>  1; if (i > 0) i < i – 1; if (i > 0) goto s5; else goto s0;
s4: output<i>  0; if (i > 0) i < i – 1; if (i > 0) goto s5; else goto s0;
s5: output<i>  1; goto s2;
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43. "Computer Design" by Sunggu Lee
Step 3: Datapath
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44. Step 4: Detailed ASM Chart
s0: setdone
c0: if (START) goto s1; else goto s0;
s1: cleardone, loadi, initbits
s2:
c1: if (greater) goto s3; else if (less) goto s4;
s3: setbit, zeroi’:(countDi), zeroi’:(goto s5), zeroi:(goto s0)
s4: zeroi’:(countDi). zeroi’:(goto s5), zeroi:(goto s0)
s5: setbit, (goto s2)
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45. "Computer Design" by Sunggu Lee
Step 5: Control Logic
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46. "Computer Design" by Sunggu Lee
Overall Design
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47. Floating-Point Adder Example
Dedicated floating-point addition unit for IEEE standard 32-bit floating-point numbers
Simplify the problem by assuming only positive floating-point numbers with no special cases
IEEE Standard for floating-point numbers based on draft proposed by Kahan et. al. in 1979.
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49. Floating-Point Addition Process
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50. "Computer Design" by Sunggu Lee
Step 1:
Pseudocode
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51. "Computer Design" by Sunggu Lee
Step 2: ASM Chart
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52. "Computer Design" by Sunggu Lee
Step 3: Datapath
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53. "Computer Design" by Sunggu Lee
Step 3: Datapath,
version 2
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Step 4: Detailed ASM
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55. "Computer Design" by Sunggu Lee
Step 5:
Control
Logic
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56. Derivation of Control Logic Equations
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57. Heuristics for Safe Design
Keep design modular and simple
Develop good documentation during design
Use design techniques to avoid clock skew
Be careful with external asynchronous inputs
Beware of noise on power and signal lines
Avoid dependencies on minimum delays
Initialize all flip-flops to known values
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58. Modular Design and Documentation
Partition complex design into separate modules
Each module should be separately testable
Insert test input paths and mechanisms to observe intermediate signal values
Start with the simplest versions of each module and follow an “iterative” design process
Keep good documentation during design process
net lists, physical placement maps
HDL (hardware description language) documents
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59. "Computer Design" by Sunggu Lee
Clock Skew
Clock skews can lead to a violation of the synchronous circuit assumption and system failure
Example of problem shown in Fig (p. 164)
Solutions
Try to equalize wire paths for all flip-flop clock inputs
Don’t use “gated” clocks
Use only positive-edge-triggered or only negative-edge-triggered flip-flops
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Asynchronous Inputs
Avoid asynchronous inputs whenever possible
Buffer remaining asynchronous inputs using FF’s
For critical signals, use debounced switches
debounced switch circuit shown in Fig (p. 167)
Un-debounced
switch circuit
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62. Noise and Drive Problems
Connect all unused inputs to Ground or Vdd
Use decoupling capacitors between Gnd and Vdd
about one mF capacitor between all Vdd and Gnd pins
perhaps one additional large (about 10 mF) capacitor
Ensure sufficient drive from chip outputs to inputs
VOHmin > VIHmin , VOLmax < VILmax ,
|IOHmax| >= S |IIHmax| at all receivers,
|IOLmax| >= S |IILmax| at all receivers
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63. "Computer Design" by Sunggu Lee
Question: How many 74ALS chip inputs can be driven
by one 74AS chip output?
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64. "Computer Design" by Sunggu Lee
Avoid delay dependencies
Don’t use “delay lines” (series of inverters used to create certain “minimum” desired delays
minimum delays cannot be relied upon
Delay-insensitive design
Flip-flop initialization
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